Senior ASIC Verification Engineer: Pre-Silicon Impact
$106.4k - $172.15kPalo Alto Networks
Palo Alto Networks, Inc. is seeking a Design Verification Engineer for the ASIC team to ensure ASICs meet industry-leading requirements for performance and reliability. This role involves defining verification methodologies and collaborating with engineers across teams to create comprehensive verification plans. Candidates should have a BS in Electrical Engineering, Computer Engineering, or Computer Science, with at least 3 years of experience in ASIC design verification. The position offers a competitive salary range from $106,400 to $172,150 per year, depending on qualifications and experience. #J-18808-Ljbffr Palo Alto Networks, Inc.
Vacancy posted 4 days ago
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