Power Delivery and Power Integrity Architect

Company Qualcomm Technologies, Inc. Job Area Engineering Group, Engineering Group > Systems Engineering General Summary Qualcomm Data Center team is developing high‑performance, energy‑efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork‑oriented individuals for our cutting‑edge technology work! Our Mission We are dedicated to transforming the industry by reimagining silicon and developing next‑generation server/compute platforms. By joining our team, you’ll collaborate with world‑class engineers to create innovative server solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing reference platforms based on Qualcomm's Snapdragon SoC, delivering a comprehensive solution that includes hardware, software, reference designs, user guides, SDKs, and more. Position: Power Delivery and Power Integrity Architect As an experienced Power delivery and power Integrity Architect (individual contributor), you will work closely with the platform team and collaborate with cross‑functional teams, including software, firmware, circuit‑design, packaging, platform engineering, memory vendors, product management, and component suppliers. You will lead the definition, analysis, simulation, and verification of end‑to‑end power delivery and power integrity (PI) solutions from die to system level—establishing droop targets, resonance phenomenon, designing and implementing the power distribution network (PDN), and validating PDN quality through lab measurements. Expected to define technical roadmaps, influence cross‑organizational strategy, and serve as a subject matter expert for Power Delivery across Qualcomm Data Center platforms. Key Responsibilities Collaborate with SoC, firmware/software, memory vendors, component suppliers, packaging, platform engineering, and system design teams to define and implement power architectures that meet internal and customer requirements. Lead voltage regulator (VR) design specification, selection, and co‑development with VR suppliers. Develop E2E VR + PDN simulation flows to reduce time to market. Perform PDN modeling, simulation, and characterization for SoC, package, PCB, VRs, and LDOs. Provide PI‑driven feedback to SoC design teams to influence decap, package, and power rail architecture. Create Power maps, Power tree and power‑flow diagrams, power budgets from die‑to system‑level. Develop and provide implementation and system efficiency guidelines. Conduct IR Drop, AC, and transient simulations and provide model‑to‑hardware correlations. Define module interfaces and formats for simulation and customer guidelines. Lead PI model creation, end‑to‑end PI simulations (thermal‑aware), and final design development taking into account effects of heat sinks and temperature effects. Leverage ML/AI‑assisted simulation techniques to streamline and automate design and analysis workflows from die to regulators. Prepare and present technical documentation and reports to stakeholders, including engineering teams, senior management, customers, and suppliers. Engage with customers and OEM partners to provide power delivery architecture guidance, PDN design guidelines, and bring‑up support. Troubleshoot system performance and identify areas for improvements. Qualifications Master's degree in Electrical Engineering or related field; experience in Power Delivery preferred. Strong experience in Power Integrity (PI). 8+ years of experience in Power delivery, board level VR design, PI analysis, simulation, and PDN measurements. Strong understanding of PI fundamentals, power supply architectures, voltage regulator technologies, chip supply design, and PDNs. Experience developing PI methodologies and PDN modeling from die to system, with model correlation and lab validation. Experience with server, HPC, or data center platform power delivery preferred. Experience with multi‑phase VR design/selection. Proficiency in PI simulation tools (e.g., Simplis/Simetrix, ADS, ANSYS SIwave, HFSS and Cadence Sigrity PowerDC/PowerSI). Hands‑on experience creating complex PI models and simulations. Proficiency with Unix/Linux environments and EDA tools using scripting. Knowledge of packaging and PCB technologies, design, and manufacturing processes. Knowledge of resonances, droops, IR Drop, cooling, temperature effects, and power consumptions. Familiarity with 2.5D/3D packaging technologies, including CoWoS, InFo, EMIB, and RDL. Strong experience in VR lab validation. Experience with electrical validation and compliance testing tools (VNAs, oscilloscopes, spectrum analyzers, TDR, differential probes). Proven ability to work independently and collaboratively within a cross‑functional team environment. Strong technical documentation skills and excellent written and verbal communication. Preferred Qualifications Ph.D. in Electrical or Computer Engineering, specializing in Power Delivery. 10+ years of experience in Power conversion, PI analysis, simulation, and PDN measurements. Experience with AI/ML‑accelerated computing platforms and their unique power delivery challenges (e.g., large transient currents, high‑bandwidth memory power integrity). Strong knowledge of voltage regulator (VR) design principles and system‑level performance. Familiarity with open compute / hyperscale server reference designs. Expertise in PDN related EM analysis. Experience with package and PCB design tools (e.g., Cadence Allegro, Sip). Proficiency in scripting languages (MATLAB, Perl, Python). Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience. OR Master’s degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. Legal and EEO Statements Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑View email address on click.appcast.io or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay Range And Other Compensation & Benefits $180,500.00 – $270,700.00. The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr Qualcomm