Senior Principal Engineer, Device Design

Job Details:Job Description: About the GroupIntel is transforming from an Integrated Device Manufacturer (IDM) to a leading global foundry service provider, offering world-class manufacturing capabilities to external customers worldwide. Our Manufacturing Development and Customer Engineering (MDCE) organization is at the forefront of this transformation-focusing on technology customization, yield improvement, performance optimization, and exceptional customer delivery.About the RoleWe are seeking a highly accomplished Senior Principal Device Design Engineer with broad semiconductor industry expertise to drive the high-level architecture, definition, and optimization of next-generation and high-volume manufacturing (HVM) semiconductor technologies. In this strategic technical leadership role, you will apply a deep mastery of semiconductor device physics to define technical roadmaps and ensure world-class performance across a diverse range of applications-including advanced logic, SRAM, low-power mobile, analog, and mixed-signal designs.Serving as a primary technical bridge between Process Integration, Yield, and Module Engineering, and collaborative product partners, you will establish the technical direction, target validations, and silicon-to-simulation accuracy across Intel's diverse technology portfolio.Key Responsibilities:Technical Strategy and Architecture Leadership: Lead cross-functional, multi-disciplinary teams in defining base and derivative semiconductor architectures-including advanced transistors, interconnects, and design rules-tailored for high-performance logic, low-power, memory, analog, and mixed-signal applications.Technical Partner and Customer Engagement: Partner directly with external customers, product design teams, and internal engineering groups to understand complex product requirements, resolve circuit-level performance/reliability/leakage trade-offs, and translate product needs into tailored silicon solutions.Technology Customization and Optimization: Drive the development and implementation of customized semiconductor features across logic and memory technologies, ensuring seamless integration with existing manufacturing processes and platforms to support specialized applications.Silicon-to-Simulation Readiness: Set and govern device and interconnect performance targets, evaluating silicon-to-simulation health, model readiness, and design feasibility for large-volume manufacturing.Cross-Functional Integration: Serve as the authoritative technical interface bridging Process Integration, Process Module, Device Physics, Yield Engineering, and Product Design to coordinate complex technology handoffs and resolve system-level constraints.Design Rule and Waiver Governance: Direct the validation and strategic waiver management processes for advanced design rules, balancing strict manufacturing compliance and yield with product design flexibility.Advanced Data Analytics: Guide the evaluation of electrical test (E-test) and yield data using advanced statistical methods and data analysis techniques to translate experimental silicon data into actionable process and design intelligence.Mentorship and Industry Thought Leadership: Provide senior technical mentorship to engineers and researchers across the organization, stay ahead of emerging semiconductor industry trends, and foster a culture of technical excellence and customer-centric innovation.Required Skills and Experience:Progressive experience in the semiconductor industry with a strong focus on CMOS device physics, device design, and semiconductor technology development.Leadership and Technology Integration: Demonstrated technical leadership within the semiconductor industry, specifically leading cross-functional teams to define, develop, and deliver advanced semiconductor technologies (covering logic, memory, or integrated architectures) and design rules into High-Volume Manufacturing (HVM).Design Rule Governance: Deep proficiency in design rule development, validation, and waiver management processes, with a strong understanding of how layout constraints impact product yield.Data and Analytical Mastery: Proven expertise in statistical data analysis, Design of Experiments (DOE), and data interpretation to evaluate test chip, E-test, and yield trends.Preferred Skills and ExperienceAdvanced and Specialty Node Expertise: Architectural experience in advanced-node transistor design and scaling, with deep experience in specialized semiconductor customization for low-power, analog, mixed-signal, and memory technologies.Physical Verification and Mask Flows: High-level familiarity with physical verification flows, Design Rule Checker (DRC) development, and mask generation concepts.Manufacturing and SPC: Extensive experience in a High-Volume Manufacturing (HVM) environment with a focus on statistical process control (SPC) and yield monitoring.Executive Communication: Exceptional verbal and written communication skills, with a demonstrated ability to influence executive stakeholders and guide collaborative partners through complex technical trade-offs.Qualifications:Master's degree in Electrical Engineering, Physics, Material Science, or a related field. PhD preferred15+ years of relevant semiconductor device and technology development experience.Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $265,480.00-374,800.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.SummaryLocation: US, Oregon, Hillsboro; US, California, Santa Clara; US, Arizona, PhoenixType: Full time