Sr. ASIC Design Verification Engineer

The application window is expected to close on: Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Participate in the ASIC design verification for Cisco high-end switching products. Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis. Construct testbenches components like scoreboard, agents, sequencers, and monitors. Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration Ensure comprehensive verification coverage through code and functional coverage implementation and review Minimum Qualifications Bachelor's degree in electrical/computer science/computer engineering/related degree and 7+ years of related experience or Master's in electrical/computer science/computer engineering/related degree and 4+ years of related experience, or PhD in electrical/computer science/computer engineering/related degree + 1 year of related experience. Prior experience in System Verilog and UVM. Experience with ASIC design and verification processes, debugging, methodology, and tools. Experience in verifying blocks/clusters or full chip level for ASIC. Preferred Qualifications Hands‑on experience with Ethernet protocols and high-speed SerDes interfaces Proficiency in Linux and programming languages such as C/C++ and/or Python/Perl Strong understanding of networking fundamentals and system-level architectures Working knowledge of PCIe and AXI protocols Experience with post‑silicon bring‑up and lab debugging Experience in data center, hyperscalers, or AI networking environments Proven contributions to industry standards or ASIC verification best practices Deep expertise in multiple protocols and large‑scale SoC architectures #J-18808-Ljbffr Cisco Systems, Inc.