Sr Principal Engineer AI/ML

We are seeking an experienced CPU IP Design Engineer. Responsible for defining, leading, and owning RTL development of our latest AI‑enabled RISC‑V CPU core. The candidate will be responsible for all aspects of the design including functional features, performance, power, and area. Responsibilities Drive the micro‑architecture and design of critical blocks of the CPU core Design of RISC‑V Vector CPU core and its custom extensions Design of AI‑enabled Matrix engine to augment the Vector CPU Explore high‑performance strategies working with the CPU modeling team Perform micro‑architecture development and specification—from early high‑level architectural exploration, through micro‑architectural research, and arrive at detailed specifications Configure design features, development, assessment, and refinement of RTL design to target power, performance, area, and timing goals Perform functional verification support and assist in the design verification strategy Assist with the verification of RTL design performance goals Partner with a multi‑functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs Required Qualifications Hands‑on working knowledge of the pipeline stages of an in‑order or out‑of‑order high‑performance CPU core Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: Instruction fetch and decode, branch prediction techniques Instruction scheduling, register renaming, Reorder Buffer (ROB) Out‑of‑order execution Integer and Floating‑point execution Load/Store execution Instruction and Data Prefetch Vector data path Cache and memory subsystems Knowledge of Cache coherency and memory consistency Knowledge of System Verilog, Verilog and/or VHDL Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Master’s degree with 10+ years of experience, PhD 5+ years of work experience Preferred Qualifications Experience with designing RISC‑V, ARM, and/or MIPS CPU Experience with hardware multi‑threading, virtualization, and SIMD designs Experience with vector and matrix‑enabled CPUs, preferably RISC‑V processors Understanding of high‑performance techniques and trade‑offs in a CPU microarchitecture Understanding of low‑power microarchitecture techniques Experience using a scripting language such as Perl or Python Understanding of CPU integration at SoC level Understanding of Safety and Security microarchitecture Salary Expected Salary Range $171,000.00 - $325,000.00. The exact Salary will be determined based on qualifications, experience and location. Accommodation If you need a reasonable accommodation for any part of the employment process, please contact us by email at View email address on click.appcast.io and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case‑by‑case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address. Equal Opportunity Statement GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory. All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law. #J-18808-Ljbffr