CPU Core Staff DFT Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.THE ROLE: As a member of the Cores DFT Team, the successful candidate will own the ATPG/DFT responsibilities for the next generation of AMD high-performance cores.  THE PERSON:  Our work is a key contributor to delivering a high-quality design and can improve AMD’s operating expenses in the millions. As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design teams, and Product engineering teams to achieve first pass silicon success.KEY RESPONSIBILITIES:  Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compressionDebug of low coverage, DRC violation fixes and coming upo with efficient and effective solutions for these issuesProficient in logic design using VerilogDebugging complex test pattern issues and simulation failuresSupport of Silicon bring up activitiesParticipating in post-silicon debugComfortable in Linux environment and writing/using scripting languages such as Perl, TCL, etc.Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test timeExcellent presentation and inter-communication skillsBachelor's in Electrical Engineering/Computer EngineeringPREFERRED EXPERIENCE:  Hands-on expertise with commercial test generation tools for large complex designsStrong fundamental knowledge of DFT techniques including JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE standards like IEEE 1149.1, 1500, and 1687.Have a good understanding of MBIST and LBIST implementationsExperience with Tessent Scan/ATPG flowsDirect experience in silicon bring-up, debug, and validation of DFT features on ATEExperience with 7nm or smaller process nodesExperience in using Agentic AI to develop flows, debug issues and compress timelines for deliverablesStrong sense of ownershipPassionate about solving complex problems and self-drivenACADEMIC CREDENTIALS:  Bachelors or Master's degree in computer engineering/Electrical EngineeringLOCATION:Santa Clara, CAThis role is not eligible for visa sponsorship.#LI-MF2#LI-HYBRIDBenefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.