RISC-V Interconnect Architect: Configurable RTL Generators
SiFive
A leading hardware technology company in Boston is seeking a staff level hardware engineer to design innovative CPU and interconnect IP. The role involves architecting and implementing advanced interconnect designs, enhancing multi-core performance, and collaborating with verification teams. The ideal candidate should possess a strong background in RTL design using Verilog/SystemVerilog, proficient programming skills, and knowledge of bus protocols. This position offers a competitive salary range and comprehensive benefits including healthcare and retirement plans. #J-18808-Ljbffr SiFive
Vacancy posted 5 days ago
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