Member of Technical Staff

Perform advanced synthesis setup by analyzing complex library collaterals, diagnosing constraint-related issues, and implementing corrections to optimize the synthesis process for IP and SoC block/toplevel designs. Ensure all Power, Performance, and Area (PPA) metrics and project schedules are met. Collaborate closely with the RTL design team to propose and implement corrections, leveraging deep technical expertise in digital design and hardware description languages. Execute end-to-end Place and Route (PnR) tasks, including floorplanning, power planning, and backend implementation for IP/SoC designs using industry-standard tools such as Cadence Innovus and Synopsys Fusion Compiler. Interface with signoff teams to provide essential design inputs, analyze feedback, and ensure successful signoff closure for IP and SoC products. Develop and deliver highly specialized scripts, comprehensive reports, and customized tool configurations for critical design signoff processes, including Electro Migration and Current Resistance (EMIR), Physical Design Verification, STA (Static Timing analysis), CLP/Low-Power Closure, Power analysis and optimization, Innovus/Fusion compiler and LEC/FV. Telecommuting and working from home permitted from anywhere in the U.S. Travel and relocation possible to unanticipated client locations throughout the U.S. Domestic travel required approximately 10% of the time to various client sites. Skills / Experience Bachelor’s or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or Computer Engineering. Minimum 5 years of experience in Design Engineering, Consulting, or equivalent using tools such as IC Compiler, Innovus, Fusion Compiler, Calibre, Star RC, Primetime, and Genus. Education and Qualifications Bachelor’s or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or Computer Engineering. #J-18808-Ljbffr