Senior SoC Architect

Architecture Lead

We are looking for a strong architecture lead to define and drive architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems. This role combines architecture definition with implementation awareness and performance ownership. The candidate will also work on platform-level performance, including building performance environments and driving closure in partnership with system architects and cross-functional teams.

We are looking for someone who can thoughtfully translate system goals into practical, scalable, implementation-ready architecture, while balancing key considerations such as performance, power, area, and schedule.

This person brings deep technical expertise and naturally fosters alignment across teams, creating a collaborative environment where ideas can thrive. Through a clear and strategic approach, they help deliver architecture that supports first-time-right integration and enables faster performance closure, ultimately contributing to more efficient and successful outcomes for the team.

The architecture must be power-optimized, highly scalable, and practical for implementation across multiple product generations.

Key Responsibilities

• Author architecture specifications for Unified Intel Chassis IP components and subsystem integration.
• Ensure architecture is implementation-aware, scalable, and power-optimized.
• Drive platform performance analysis and closure, including bottleneck identification and optimization.
• Build and enhance platform performance environments, models, and benchmarking flows.
• Define and validate end-to-end QoS, arbitration, and routing strategies for high-bandwidth traffic.
• Partner with system architects, RTL/design, verification, firmware/software, and performance teams to align architecture with product goals.
• Define architecture trade-offs, assumptions, interfaces, and measurable success criteria.
• Support debuggability, safety, reliability, and serviceability requirements in architecture definition.

UIC IP Scope

• UIC Coherent and Non-Coherent Fabric
• Protocol Adaptors for industry-standard protocols (AXI, CHI, CXL, UAL, etc.)
• Cache Controller IP
• MMU / IOMMU IP
• Clock, Reset, and Power Management IP
• Debug and Analytics IP
• Security and Access Management IP

Qualifications:

Minimum qualifications, you must possess the below minimum qualifications to be initially considered for this position.

• Bachelor’s degree in a specialized field such as Computer Science, Electrical Engineering, or related discipline along with 6 or more years of relevant technical experience.
• OR MS degree in a specialized field such as Computer Science, Electrical Engineering, or related discipline along with 4 or more years of relevant technical experience.

• Experience listed above should be a combination of the following:
• in SoC IP architecture for high bandwidth interconnect and/or subsystem design.
• writing high-quality architecture specifications used by design and verification teams.
• hands-on with power optimization techniques.
• defining architecture requirements, interface contracts, performance targets, and power/performance/area trade-offs.

• 1+ years of experience working:
• with AMBA protocols, especially AXI, CHI, and APB.
• collaborating across architecture and implementation teams.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Working with AI tools to develop machine readable specification documents for Spec2Silicon fast and reliable execution.
• Deep understanding of coherency concepts and CHI architecture.
• Proven expertise in arbitration and routing algorithms, end-to-end QoS (Quality of Service), and high-bandwidth low latency, scalable designs.
• Experience with fabric-based scalable platforms across multiple markets or generations.
• Exposure to performance modelling, simulation, and data-driven architecture tuning.
• In-depth understanding of cache architecture and memory management/address translation MMU, IOMMU.
• Familiarity with security architecture and access control frameworks in SoC platforms.
• DVFS and Distributed power management.
• Background in debug, safety, and RAS architecture.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

Business Group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $170,500.00-315,490.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.