Senior ASIC Design Engineer - DSP/SerDes for Optical Systems

Celero Communications seeks a Senior ASIC Design Engineer to develop advanced ASICs for high-speed optical communication systems. You will design high-performance digital circuits and collaborate with DSP, Analog, and SerDes teams to integrate complex functionality. Responsibilities include RTL design, synthesis, timing analysis, CDC, and PPA optimization, with opportunities to lead architecture, verification, and silicon bring-up while creating automation scripts in Python or Tcl.