Lead DFT Architect for Photonic AI ASICs
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Neurophos is hiring a DFT Architect to own design-for-test for our electronic ICs. You will set the DFT strategy for the full chip, own coverage assessment and signoff, and collaborate with RTL and physical design teams to build testability in from the start. This is our first dedicated DFT hire, shaping the testing approach and growing the team. You will define test requirements with the analog team, drive system-level wafer and package test plans, and push for rapid, production-ready test #J-18808-Ljbffr Socket.dev
Vacancy posted 3 days ago
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