Logic Design & Verification Engineer (RTL, UVM, Memory)
FLC Technology Group
FLC Technology Group in Santa Clara, California, is looking for candidates with expertise in logic design and verification. The role involves responsibilities for design, verification, and presenting documents. Candidates should possess strong skills in Computer Architecture, particularly in simulation tools and out-of-order execution. Applicants should have an MS or BS in EE/CS combined with two years of experience, showcasing proficiency in Verilog and System Verilog with experience in FPGA/emulator environments. #J-18808-Ljbffr
- Logic design/synthesis/timing analysis or Logic Verification/Test Coverage Responsible for design... ...hazard, cache/memory subsystems, and simulation... ..., RTL logic implementation... ...Verilog Verification engineers: must have experience... ...code coverage and UVM Team player and an...SuggestedWork at office
$138k - $198k
Google Inc. is seeking a Verification Engineer in Mountain View, CA. In this role, you’ll verify complex digital design blocks, utilizing SystemVerilog and UVM to enhance verification environments and ensure functionally correct designs. The qualified candidate will have...Suggested- ...development of DRAM Test Engine, Prefetch Engine, and Memory Controller for... ..., Synopsys VCS, UVM tools, and... ...with design and micro-architecture... ...the design Apply verification methodologies to... ...experience in digital logic systems. A... ...and debugging; RTL simulation and debugging...Suggested
- ...Performs functional verification of graphics logic components, including... ...and display, to ensure design will meet... ...with GPU architects, RTL developers, and physical... ...electronics, computer engineering, or related engineering... ...System Verilog, OVM and UVM Hands on verification...SuggestedLocal area
$181.1k - $318.4k
...telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying... ...Engine hardware - DRAM subsystem, memory controller logic - Encode and Decode systems for... ...of verification methodologies like UVM Experience with C/C++, assembly is...SuggestedRelocation$128k - $312k
...Comprising brilliant engineers and visionaries, the team designs and develops... ...looking for an ASIC RTL Design Engineer specializing... ...interconnect and memory systems to drive... ...system architects, verification engineers, physical... ...methodologies (e.g., UVM) and scripting (...Hourly payTemporary workFlexible hoursNight shift$138k - $198k
...Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science,... ...experience. 4 years of experience with design verification. Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs. Preferred qualifications...Full timeWorldwide$164.47k - $269.1k
...work every single day to design and manufacture... ...Responsibilities Performs functional logic verification of an integrated SoC... ...full chip architects, RTL developers,... ...degree in Electrical Engineering, Computer Science, or... ...in the following: OVM/UVM methodologies and System...Local area$138k - $198k
...degree in Electrical Engineering, Computer Science, a... ...verifying digital logic at RTL using SystemVerilog.... ...creating and utilizing UVM-based verification environments.... ...standard interfaces and memory system architecture.... ...of complex digital design blocks by analyzing...Full timeWorldwide- ...technology and humans designing meaningful and sustainable... .... Job Title FPGA RTL design and Board... ...skilled Senior FPGA Design Engineer with 7 to 15 years of experience... ...yr in FPGA RTL design, Verification and board level... ...Should have worked in SV- UVM, Verilog, VHDL...Work experience placement
- ...every single day to design and manufacture silicon... ...Performs functional verification of mixed signal logic components,... ...analog architects, RTL developers, and physical... ...degree in Computer Engineering/Computer Science/Electrical... ...Verilog and OVM/UVM or MS degree in Computer...InternshipLocal areaImmediate startShift work
$136k - $218.5k
...motivated and creative Senior Verification Engineer for our Tegra SoC Memory Subsystem IP verification... ...you will partner with the design and architecture teams to... ...coverage of all the RTL which you will verify. Work... ...Background with System Verilog and UVM based methodology for ASIC...- Apply advanced verification methodologies to verify memory subsystem designs of the computer systems, including... ...test plans; build UVM‑based constrained random... ...s degree in Electrical Engineering and four years of experience... .../SystemVerilog/UVM; RTL simulation tools (...
$163k - $237k
Design Verification Engineer, Digital Signal Processing Google - Sunnyvale, CA, USA... ...communication systems, or arithmetic logic blocks. Experience with... ...Verification comparing RTL against MATLAB or C++ golden... ...environments using SystemVerilog and UVM for individual DSP blocks (e...Full timeWorldwide$167.1k - $250.7k
...Technologies, Inc. Job Area: Engineering Group, Engineering... ...engineers for CPU RTL development... ...and RTL Design Engineer, you will... ...goals. Functional verification support. Help the... ...prefetching, cache and memory subsystems. Knowledge... .... Knowledge of logic design principles...Work experience placementWork from home- ...an adaptive, self‑motivative design verification engineer to join our growing team. As... ...teams PREFERRED EXPERIENCE: RTL spyglass/lint RTL power... ...optimization (PowerArtist) IP Logic design Good at C/C++ Familiarity... ...verification libraries like UVM Experience/Background on...
$126.8k - $220.9k
...energy-efficient design and new technologies... ...integrated engineering team spanning RF/Analog... ...and design, VLSI/RTL design and integration... ...Emulation, Design Verification, Test and... ...area efficient RTL logic design, and DV support... ...Familiarity with UVM DV environment and...Relocation- ...the endless possibilities of AI. Role Design Verification Engineer, Senior Staff Location Hybrid, working... ...industry’s first highly programmable in‑memory computing architecture that applies to... ...of verification methodologies such as UVM/OVM etc. Hands on ASIC-SoC Design...3 days per week
$110k - $300k
...innovations in In-Memory Computing. Leveraging... ...talented team of engineers and industry-... ...Collaborate with design engineers and architects... ...the SoC design verification Build and maintain... ...depth knowledge of UVM/OVM, Semiformal Verification... ...at both of RTL level and post-P&R...- ...A leading semiconductor company is seeking a Design Verification Engineer in Santa Clara, CA. This role involves developing and maintaining verification tests, building support components for next generation IP, and providing technical support to different teams. We are...
- ...a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll... ...scratch using advanced methodologies like UVM (Universal Verification Methodology).... ...ability to debug complex digital logic and verification environments. Preferred...
$147.4k - $272.1k
...be at the center of a chip design effort interfacing with many... ...Description As a CPU Top-Level Design Verification Engineer owning the verification... ...verification engineers and RTL designers on defining... ...design, cache hierarchies, and memory systems RTL development - Experience...Relocation$126.8k - $220.9k
...concept through production. As a Wireless Design Verification Engineer, you'll ensure first‑time‑right... ...feature closure. Develop comprehensive UVM testbench environments and BFMs spanning... ...testing, functional coverage analysis, and RTL simulation workflows. Strong problem‑...WorldwideRelocation- ...) Degubbing and development UVM, SystemVerilog exp 8 to 10 years... ...Description As a GPU Design Verification Engineer, your talents will ensure the... ...root cause along, working with RTL and reference modeling teams... ...of micro‑architecture, logic design, FSMs, arithmetic datapath...Local areaRemote work3 days per week
- ...Staff Logic Design Engineer page is loaded## Staff Logic Design Engineerlocations... ...Responsibilities*** **RTL Design &... ...protocol decoders.* **Verification & Debug** + Build SystemVerilog/UVM testbenches for block and... ...**AXI interconnects**, memory controllers, and high-speed...
$136k - $265k
...NVIDIA Gruppe is seeking a Senior ASIC Design Engineer for its Memory Controller team in Santa Clara, California. This role involves collaboration with architects and engineers to design and verify micro-architectures for memory subsystems. The ideal candidate will have...$70 - $100 per hour
...Santa Clara, United States Sector: Engineering Salary: $70.00 to $100.00 per hour Design Verification Engineer - CPU Subsystem Looking... ...in System Verilog (SV) & UVM, with a focus on developing verification... ...functional verification at the RTL level. The ideal person would...Hourly payNight shift$141.91k - $269.1k
...Description: The Role and Impact As an IP Design Verification Engineer, you will play a pivotal role in Intel... .... Collaborate with architects, RTL developers, and physical design teams... ...with a strong understanding of OVM and UVM methodologies. Experience in functional...Local area$147.4k - $272.1k
...be at the center of a chip design effort collaborating with all... ...quickly. Description As a CPU Verification Engineer owning the verification of a... ...with architecture and RTL designers on verifying the functionality... ...Experience in digital logic design, chip architecture,...Relocation$126.8k - $220.9k
...that Apple’s Silicon Engineering Group has embarked upon... ...craft highly reusable UVM TB, implement effective... ...DV methodology, verification on accelerated platforms... ...etc. Description As a Design Verification Engineer... ...Timer, high BW DMAs, memory management schemes, low...RelocationFlexible hours
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