Staff/Senior Staff GPU Engineer - Shader RTL & Microarchitecture

Job Description

Position: Staff/Senior Staff GPU Engineer - Shader RTL & Microarchitecture

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Location: San Diego, CA (4 days onsite)

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Employment Type: Full-Time

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Overview

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In partnership with a top-5 semiconductor company's leadership in SoC design, their GPU IP team is committed to developing industry-leading, feature-rich, and highly PPA-competitive graphics IP. Their GPU technology is deployed across flagship and mainstream mobile SoCs and is also a foundational technology for adjacent markets including laptops, IoT, AI, VR/AR, automotive, and custom ASIC applications.

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The team is expanding and hiring top GPU talent across multiple disciplines, including architecture, microarchitecture, RTL design, software drivers, compiler technology, performance modeling, power optimization, and silicon validation.

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Position Summary

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We are seeking a Staff / Senior Staff GPU Engineer specializing in Shader System RTL Design and Microarchitecture to help define, design, and deliver next-generation GPU IP. The ideal candidate will have strong hands-on experience in GPU shader subsystem microarchitecture, RTL implementation, performance analysis, functional debug, and PPA optimization.

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In this role, you will drive the design and optimization of GPU shader systems, including shader core pipelines, thread/warp/wave scheduling, instruction dispatch and issue, execution pipelines, register files, operand collection, scoreboard and dependency management, load/store interaction, cache/memory interfaces, synchronization, and cluster-level integration.

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You will collaborate closely with architecture, compiler, software driver, performance modeling, verification, physical design, and post-silicon teams to deliver best-in-class GPU IP for mobile, automotive, laptop, IoT, AI, VR/AR, and ASIC markets.

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Key Responsibilities

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• Define, develop, and own GPU shader subsystem microarchitecture specifications.
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• Lead RTL design for shader-related blocks, including shader pipelines, instruction issue, operand collection, register files, dependency tracking, and pipeline control.
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• Collaborate with architecture and compiler teams to translate ISA behavior, API requirements, shader workloads, and performance targets into efficient hardware designs.
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• Analyze GPU workloads and performance data to improve occupancy, throughput, latency hiding, register pressure, and power efficiency.
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• Support the full GPU IP lifecycle, including microarchitecture definition, RTL coding, lint/CDC/RDC cleanup, verification support, synthesis, timing closure, tape-out, bring-up, and post-silicon debug.
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• Partner with verification teams on test plans, coverage, assertions, debug strategies, and directed/random test scenarios.
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Required Skills & Experience

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• BS, MS, or PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field, or equivalent practical experience.
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• 8+ years of experience for Staff level, or 10+ years for Senior Staff level, in RTL design, microarchitecture, or architecture for GPU, graphics, processor, AI accelerator, DSP, or high-performance SoC subsystems.
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• Strong hands-on experience with SystemVerilog, Verilog, VHDL, C/C++, and scripting languages such as Python, Perl, Tcl, or shell.
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• Proven experience designing complex RTL blocks with strong understanding of timing, area, power, clocking, reset, CDC/RDC, low-power design, and synthesis constraints.
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• Solid understanding of computer architecture, GPU architecture, processor pipelines, parallel execution models, memory hierarchy, interconnects, and performance/power trade-offs.
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• Experience with RTL quality flows including lint, CDC, reset analysis, synthesis, formal checks, assertions, waveform debug, and regression debug.
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• Ability to work effectively with architecture, verification, physical design, software, compiler, performance, and post-silicon teams.
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Preferred Skills

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• Deep knowledge of GPU shader architectures, including SIMT/SIMD execution, instruction issue, register files, operand collection, execution pipelines, and latency hiding.
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• Hands-on experience with one or more shader subsystem areas: pipeline design, instruction fetch/decode/dispatch/issue, register file banking, or dependency tracking.
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• Experience with GPU graphics and compute workloads such as vertex, pixel/fragment, compute, mesh, geometry, tessellation, ray tracing, or AI/ML shaders.
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• Knowledge of GPU ISA, shader compiler interaction, instruction scheduling, register allocation, occupancy, and compiler-hardware co-optimization.
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• Experience with mobile GPU design, tile-based rendering, unified shader architectures, and low-power design.
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Please reach out to View email address on ziprecruiter.com for more details or to express interest in the role.