Senior Mask Layout Design Engineer

Responsibilities Collaborate with a multi-disciplinary team of circuit designers and mask designers. Perform physical layout for digital and mixed‑signal functions such as clock generators, op‑amps, sensors, security circuits, power delivery circuits in state‑of‑the‑art sub‑micron CMOS technologies using Cadence tools. Work with ASIC and mixed‑signal engineers to customize designs for integration in VLSI products. Conduct floor planning, custom layout, and verification against design rules and schematics. Handle fill, post‑processing, DRC mitigation, and foundry interactions. Qualifications BS in Electrical Engineering (or equivalent experience). At least 7+years of hands‑on layout design experience. Deep understanding of analog circuit layout concepts in sub‑micron CMOS technologies; validated experience with Cadence custom circuit design tools, especially Virtuoso. Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre. Leadership experience mentoring and assisting junior mask designers, implementing standard processes for the team, and maintaining checklists for optimal layout design. Strong communication skills and experience collaborating with diverse teams across geographies and time zones. Interpersonal skills and positive energy to work effectively in a team. Proficiency in scripting languages such as Perl or Python (a plus). Knowledge of layout automation (a definite plus). Compensation and Benefits Base salary range: USD132,000–207,000. Eligible for equity and other benefits. Equal Opportunity Employer Statement NVIDIA is committed to fostering a diverse work environment and is an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law. #J-18808-Ljbffr NVIDIA Gruppe