Senior High-Speed Analog Layout Engineer
eTeam
eTeam seeks an experienced High-Speed Analog Layout Engineer to design physical silicon layouts for high-frequency mixed-signal blocks. You will handle floor planning, block integration, and co-design with packaging considerations. Ideal candidates have 5–12+ years in deep sub-micron CMOS/FinFET nodes, with critical experience at N3 and N5 nodes, and a track record addressing LOD, WPE, LDE and robust noise control. #J-18808-Ljbffr eTeam
Vacancy posted 4 hours ago
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