Principal Electrical Engineer-FPGA Verification

Principal Level Electrical EngineerThe Radar Digital Products (RDP) Department at Raytheon is seeking an experienced Principal level Electrical Engineer to verify FPGA based designs for control and/or signal processing radar applications.This position can be for the Tewksbury, MA location or the Marlborough, MA location.What You Will DoOwn or contribute to the successful completion of FPGA-based designs, on time and on budgetVerify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage using UVMCreate complete documentation including verification plan and reportDemonstrate self-motivation, with little supervision requiredWork cooperatively with systems, hardware, software engineers, and program management to ensure product successSupport internal and external technical reviewsQualifications You Must HaveTypically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experienceDigital design verificationStrong proficiency in SystemVerilog for both design and verification (interfaces, clocking blocks, assertions)Hands-on experience building UVM-based testbenches from scratch, including env, agent, scoreboard, and coverage componentsSolid understanding of constrained-random verification and functional coverage methodologyFamiliarity with AXI, PCIe, Ethernet, DDR protocols.Experience with industry-standard simulators (e.g., Questa, VCS, Xcelium)Experience with regression management and debug of complex, intermittent failuresAbility to develop and maintain verification plans tied to design specifications and coverage closure criteriaExperience with version control systems (e.g., Git, ClearCase, SVN) in a team-based development environmentQualifications We ValueProficiency with Git. Branching strategies, pull requests, and collaborative workflowsExperience with UVMF (UVM Framework) for structured, reusable testbench developmentFamiliarity with Vivado and Quartus FPGA simulation flowsExperience with scripting languages (Python, Tcl, Perl) for test automation and toolingExperience designing FPGAs using VHDLFamiliarity with SLURM workload manager for job scheduling and compute cluster resource managementPrior experience mentoring junior verification engineersExisting DoD security clearance