DFT Application Engineer

Job Details:Job Description: About Intel Foundry ServicesIntel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.Position OverviewWe seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role supports Aerospace, Defense, and Government (ADG) customers in achieving successful tape-outs while ensuring the highest quality standards through comprehensive DFT solutions and customer engagement.Key ResponsibilitiesCustomer Technical Support & CollaborationProvide comprehensive DFT tool/flow/methodology support to address customer issues and challenges, ensuring successful tape-outs and maximum customer satisfactionWork closely with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors to resolve complex technical issuesDeliver customer-facing technical support and guidance on DFT implementation strategiesDFT Methodology & Quality LeadershipDrive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementationsCollaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM physical implementation, validation, and timing signoffDevelop and optimize DFT insertion flows for advanced CMOS processes and multi-die designsTechnical Content Development & TrainingDevelop application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teamsCreate best practice guidelines and methodology documentation for DFT implementation across various design complexitiesSupport knowledge transfer and capability building for both internal teams and customer organizationsEssential Skills & AttributesCustomer-Focused: Strong customer-oriented attitude and mindset with commitment to customer successSelf-Motivated: Self-driven and results-oriented with ability to manage multiple complex tasks effectivelyCollaborative: Excellent teamwork skills to drive innovative solutions for customer design implementation challengesAnalytical: Strong analytical problem-solving capabilities for complex DFT challengesCommunication: Effective communication skills with experience in collaboration, active listening, and providing constructive technical feedbackQualifications:The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum QualificationsUS Citizenship requiredAbility to obtain US Government Security ClearanceBachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field3+ years of experience with advanced CMOS processes (22nm and below)3+ years of combined experience in the following: implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC level2+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting)Preferred QualificationsActive US Government Security Clearance with a minimum of Secret Level.Post-graduate degree in Electrical/Computer Engineering or STEM-related fieldHands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, ReliabilityProficiency with major EDA tools for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die designsExperience building/developing quality DFT/DFX insertion flow and ATPG validation flowExperience providing technical direction to engineering teams and customer supportCustomer-facing experience in technical rolesExperience with state-of-the-art process technology (7nm and below) and PDK-based technology evaluationWhat We OfferOpportunity to work with cutting-edge DFT technologies for aerospace, defense, and government applicationsDirect customer engagement and technical leadership in advanced semiconductor designAccess to Intel's most advanced foundry technologies and comprehensive EDA tool suitesCompetitive compensationProfessional development in DFT methodologies and foundry servicesDirect impact on national security through advanced semiconductor technology solutionsJob Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.SummaryLocation: US, Arizona, Phoenix; US, California, Santa Clara; US, Oregon, HillsboroType: Full time