Full Chip Integration Engineer

Job Description

Job Description

Title : Integration Engineer

Pay Rate: $80/hr. - $120/hr.

Location: San Jose, CA

Duration: 6 Months

Responsibilities:

• Integrate digital block GDS/OASIS databases into the full-chip layout.
• Perform top-level physical integration, layout assembly, and connectivity checks.
• Own bump placement, bump assignment, and bump/RDL routing.
• Develop and run top-level DRC/LVS decks and drive physical verification closure.
• Debug and resolve full-chip DRC/LVS violations, connectivity issues, and integration errors.
• Coordinate with package design, digital implementation, IP, and foundry teams.
• Perform chip-package interface checks, bump map verification, and other tapeout signoff checks.
• Prepare and validate final full-chip GDS/OASIS and signoff deliverables for tapeout.

Required Qualifications:

• Strong hands-on experience in full-chip physical integration and hierarchical GDS/OASIS assembly.
• Proven experience with bump placement/routing and top-level DRC/LVS signoff.
• Proficiency with tools such as Cadence Innovus, Siemens Calibre, Synopsys IC Validator, or equivalent.
• Experience with package integration, foundry design rules, and tapeout flows.
• Ability to independently drive full-chip integration and signoff to completion.
• Tcl/Python scripting experience is a plus.