Physical Design Engineer

Build the Silicon That Shapes What's Next
We are partnering with an advanced semiconductor innovation team focused on next-generation high-speed interconnect technologies, AI infrastructure, and future compute architectures. They are seeking a senior-level Staff Physical Design Engineer to take full ownership of the physical implementation of a cutting-edge mixed-signal PHY test chip from synthesized netlist through GDSII tape-out.
This is not a support role or a traditional staff augmentation engagement. This is an opportunity for an experienced engineer to own a technically challenging implementation effort within a lean, elite engineering environment where your expertise directly influences silicon success.
The project centers on a 36 I/O full-duplex die-to-die interconnect PHY characterization chip designed to validate novel signaling architectures and generate silicon data that will help shape future interconnect scaling strategies.
You'll work side-by-side with highly respected analog designers, digital chip leadership, and an experienced layout specialist on a focused tape-out mission with clear goals and meaningful technical depth.


Job Title: Physical Design Engineer

Location: Minneapolis, MN

Pay Range: $65

What You'll Be Doing
You will own the complete back-end implementation flow for the test chip, including:

• Full-chip floorplanning and mixed-signal partitioning
• Power distribution and power integrity implementation
• Place & route execution using Cadence Innovus
• Static timing analysis and timing closure using Cadence Tempus
• IR drop and electromigration analysis
• DRC/LVS/ERC sign-off using Mentor Calibre
• Scan insertion and DFT coordination
• Tape-out preparation and foundry coordination
• ECO management and implementation optimization
• Documentation and knowledge transfer at project close

This is a deeply technical environment involving:

• Analog/digital co-design challenges
• High-speed I/O implementation
• Complex macro integration
• Constrained mixed-signal floorplanning
• Full-chip sign-off ownership

What We're Looking For

Required Experience

• BS, MS, or PhD in Electrical Engineering or related field
• 8+ years of physical design experience
• Experience leading at least one complete tape-out as primary or lead PD engineer
• Strong hands-on expertise with:
  • Cadence Innovus
  • Cadence Tempus
  • Mentor Calibre
• Experience with:
  • MMMC timing closure
  • OCV/AOCV analysis
  • ECO flows
  • Hard macro integration
  • Mixed-signal floorplanning
• Strong debugging and problem-solving skills
• Ability to operate independently in a fast-moving environment

Preferred Experience

• Mixed-signal or analog-adjacent chip implementation
• High-speed interface or PHY design environments
• Power integrity tools such as Voltus or Redhawk
• UPF/CPF multi-voltage implementation
• Familiarity with Synopsys ICC2
• Prior startup or contractor experience

The Type of Engineer Who Thrives Here
This role is ideal for someone who:

• Enjoys broad technical ownership
• Likes solving difficult implementation problems
• Takes initiative and drives closure independently
• Communicates effectively across design disciplines
• Thrives in lean, highly collaborative teams
• Finds tape-out execution energizing, not exhausting

You'll have direct visibility into critical design decisions and the opportunity to make a meaningful technical impact without layers of process slowing things down.

Why Engineers Are Interested in This Opportunity

• End-to-end ownership from floorplan to tape-out
• Technically rich mixed-signal implementation work
• Collaboration with highly experienced silicon experts
• Lean team with fast decision-making
• Opportunity to influence future interconnect technologies
• Clear project scope and defined deliverables
• High-impact contract engagement with meaningful autonomy

If you're a senior physical design engineer who enjoys owning implementation challenges from start to finish and wants to contribute to advanced silicon development in a high-accountability environment, we'd love to connect with you.


Upon completion of waiting period, consultants are eligible for:

• Medical and Prescription Drug Plans
• Dental Plan
• Vision Plan
• Health Savings Account
• Health Flexible Spending Account
• Dependent Care Flexible Spending Account
• Supplemental Life Insurance
• Short Term and Long Term Disability Insurance
• Business Travel Insurance
• 401(k), Plus Match
• Weekly Pay

About ManpowerGroup, Parent Company of: Manpower, Experis, Talent Solutions, and Jefferson Wells.

ManpowerGroup® (NYSE: MAN), the leading global workforce solutions company, helps organizations transform in a fast-changing world of work by sourcing, assessing, developing, and managing the talent that enables them to win. We develop innovative solutions for hundreds of thousands of organizations every year, providing them with skilled talent while finding meaningful, sustainable employment for millions of people across a wide range of industries and skills. Our expert family of brands - Manpower, Experis, Talent Solutions, and Jefferson Wells - creates substantial value for candidates and clients across more than 75 countries and territories and has done so for over 70 years. We are recognized consistently for our diversity - as a best place to work for Women, Inclusion, Equality and Disability and in 2023 ManpowerGroup was named one of the World's Most Ethical Companies for the 14th year - all confirming our position as the brand of choice for in-demand talent.