VDHL Design Engineer

Job Description

Job Description

VHDL Design Engineer

All candidates must be eligible to obtain a United States Security Clearance
Candidates must be able to commute to Cincinnati, Ohio on a regular basis if not local

The FPGA/ASIC Firmware Engineer is expected to design, architect, and implement waveforms and digital signal processing (DSP) algorithms using VHDL or Verilog targeting software defined radio (SDR) hardware. Firmware development is applied to high complexity and high throughput implementations with a focus on VHDL, code re-use, fixed-point modeling, low power design, system integration, test automation, FPGA/ASIC IP Core development and product test/support while leveraging advancements in systems-on-chip (SoCs), synthesis tools and SDR hardware. We are looking for individuals who have demonstrated abilities in innovative thinking and versatility in their jobs with experience in the following: FPGA/ASIC architecture design, simulation and verification, MATLAB or C/C++ familiarity and proposal, report and system/product specification development. The individual will work within a team environment to achieve high efficiency in solving our customer's formidable challenges and meeting our customer's requirements objectives.

Roles and Responsibilities

• Demonstrated leadership skills/experience in digital design engineering, HDL coding, implementation of waveforms/modems and digital signal processing, performance/test analysis and technical team leadership.
• Implementation of waveforms/algorithms in VHDL (preferred) or Verilog.
• Experienced with lab and field testing, test equipment such as signal generators, spectrum analyzers, and digital logic analyzers.
• Familiarity with signal processing systems, terrestrial/airborne/satellite transmitter and receiver design including acquisition, tracking and demodulation, MATLAB, C/C++, synthesis, verification/acceptance testing.
• Individuals with a background developing solutions for military/DoD customers is plus.
• Provide concise explanation and design documentation of developed firmware implementation to enable team members to support system integration.
• Identification, development and implementation of FPGA/ASIC IP Cores.
• Deliver effective briefings and to work efficiently in a multidisciplinary team environment.
• Travel to support events such as customer site support, training seminar, proposals.
• Proactively ensure a safe work environment and adhere to company policies and procedures.

Qualifications

• Bachelor's degree or Master's degree, preferable with work experience, in Electrical/Computer Engineering specializing in wireless communications/DSP, system design and new product development.
• Must be proficient in VHDL.