Signal Integrity Validation Internship (Summer 2025)

Cadence Silicon Solutions Group (SSG) develops industry‑leading Digital IP (Intellectual Property), from RISC‑V processor cores to DSPs to Memory Controllers and IO solutions. Our configurable and extensible IP solutions are poised to meet the demands of next‑generation applications such as intelligent IoT Devices and ML/AI edge inference. Signal Integrity Validation Internship In this position, you will be working with a team of Signal Integrity Engineers. Your scope of responsibilities will include but are not limited to: Performing modeling and simulation of high‑speed interface interconnects/channel. Working in lab to perform measurement, and correlating measurements to simulations. Working with silicon designers, platform designers, package designers, electrical validation teams, etc. to support interconnect and interface performance requirements. Contributing to package and platform design guideline development. Reviewing and evaluating package and board design and providing review feedback; Electrical modeling and simulation of high‑speed IO interconnects, such as DDR. Development of package and platform design guidelines. Definition and evaluation of circuit design features required to support interconnect performance requirements. Creation of signal measurement test plans and review of measurement results. Correlation of measurements to simulations, and modification of models as required. Support signal integrity tool and methodology development. Position Requirements Currently enrolled in MSEE or equivalent. Understanding of electro‑magnetic principles for digital signal integrity. Experience with signal integrity and electro‑magnetic simulation/analysis tools such as Ansys HFSS and Designer, CST Microwave. Experience with signal integrity measurements and debugging with TDR, VNA, pattern generators, error detectors and similar measurement equipment. Understanding of frequency‑domain and time‑domain component and circuit characterization. Understanding of test and calibration methods. Experience in component design and application of high‑speed cables/connectors into communications equipment is a plus. Experience with Cadence tools, Matlab, ADS, and HSPICE is a plus. The hourly range for California is $31.63 to $58.75 per hour. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the hourly range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr Cadence Design Systems