Senior FPGA Architect - MEMS Timing, Equity & Bonus

SiTime-Corporation is seeking a Principal FPGA Design Engineer based in Santa Clara, CA. This role involves designing FPGA-based platforms and leading technical initiatives to support our MEMS timing products. Candidates should have over 10 years of experience in FPGA architecture, along with expertise in Verilog/VHDL and high-speed interfaces. We offer a competitive salary range of $164,800 - $226,600, plus bonuses and equity grants. Additional benefits include health and wellness plans, a 401k, and more. #J-18808-Ljbffr Sitime-Corporation