ASIC and Logic Design Engineering Manager (Teradyne, North Reading)

ASIC and Logic Design Engineering Manager (Teradyne, North Reading) Date: Mar 24, 2026 Location: North Reading, MA, US We are the global test and automation specialists, powering next‑generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions helps manufacturers develop and deliver products quickly, efficiently and cost‑effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high‑performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees and communities thrive. Opportunity Overview The Logic Design Manager is responsible for leading a team of developers in designing and verifying FPGA’s for Teradyne Compute Test Division’s next‑generation products. In this role you will lead a team of ~4‑6 engineers in a fast‑paced environment to help the organization meet key business needs. Requires close collaboration with the other FPGA design and verification managers and with other engineering disciplines including mixed‑signal ASIC design, circuit board design, software and systems engineering to specify and implement new products. You should have hands‑on experience with complex FPGA (and preferably digital ASIC) SOC designs for real‑world products. You also should have a proven track record of managing engineering teams toward timely deliverables and successful project completion. Responsibilities Lead multiple simultaneous (typically 2-3) FPGA or digital IP development projects. Typically include oversight of some remote resources. Plan and track project schedule and budget. Manage project staffing levels including both full‑time and contract resources. Represent the FPGA team on project core teams and at program reviews. Contribute to FPGA implementation (i.e., code RTL blocks) as needed. Provide technical support for HW sustaining issues. Set goals, provide coaching and manage compensation of a 4‑6 person team. Contribute to FPGA team process improvement initiatives. Collaborate with other engineering and business disciplines to ensure that FPGA and IP deliverables satisfy all product requirements. All About You We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position. Qualifications BSEE or MSEE and 12+ years of relevant experience in Digital FPGA design and integration (Digital ASIC experience is a plus). Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation and lab validation to production release. Extensive experience coding RTL (Verilog preferred). Extensive experience using digital simulation tools (Cadence preferred). Extensive experience using static timing analysis tools. Experience designing with the following: PCIe, DDR3/4/5, AXI, Ethernet, SPI, SERDES. Experience with either AMD or Altera FPGAs and development tools (Vivado/Quartus), preferably both. Experience using digital design quality tools e.g. LINT, CDC. Experience with bug tracking tools (Jira, etc.). Experience with source control systems (ClearCase, Git, CVS) and continuous integration. Familiarity with digital verification tools and methodologies (preferably UVM). Experience with project scheduling tools (e.g. Microsoft Project). Experience with embedded processors and digital signal processing is a plus. Experience with high‑level programming languages (C, C++) is a plus. Excellent presentation and communication skills. Preferred: Experience developing hardware for automated test equipment is a plus. Preferred: 2-3 years of experience as a first‑level manager of an engineering team. Compensation The base salary range for this role is $155,500 - $248,700. This range is a good‑faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan This job is eligible for discretionary bonus(es) based on financial performance. Benefits Teradyne offers a variety of robust health and well‑being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details. Job Segment Electrical Engineering, Testing, Design Engineer, Embedded, Engineering Manager, Engineering, Technology #J-18808-Ljbffr Teradyne