REQ: Logic (RTL) Design Engineer in Santa Clara, CA (Onsite)

Hi,

One of our clients is looking for Logic (RTL) Design Engineer in Santa Clara, CA (Onsite)

Title: Logic (RTL) Design Engineer

Location: Santa Clara, CA (Onsite)

Duration: 4+ Months

C2C or W2 Only

Roles/Responsibilities:
The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals







Requirements:

• Bachelor's degree in electrical or computer engineering or related field
• 7+ years of experience in Logic (RTL) Design

Preferred Qualifications:

• Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Experience with advanced peripheral bus IP's such as GPIO, UART, SPI, SW, JTAG, and I2C.
• Strong fundamentals in VLSI design
• Strong problem-solving and data analysis skills
• Strong skills using scripting languages such as Perl, TCL, Python.
• Excellent interpersonal skills and able to work with remote teams
• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
• Knowledge of low-speed bus protocols (AMBA/OCP) and high-speed serial protocols (PCIe/USB/Ethernet) will used at various stages of the design
• Develop HW architecture from specification documents.
• Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
• Develop and execute low power design (UPF/CPF).
• Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc
• Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties)
• Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.
• Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
• Take ownership of tasks and drive tasks to closure.

Synopsys/Cadence EDA Tools (Preference: 5)
Design Compiler (Preference: 5)
Spyglass Tools (Preference: 5)
Python (Preference: 3)

Interested candidates, please send your updated resume to: View email address on us.fitly.work

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