Lead ASIC DFT Engineer

10+ years of hands‑on experience in ASIC Design‑for‑Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post‑silicon validation, along with the ability to lead cross‑functional debug efforts and drive resolution of critical silicon issues. Key Skills Required Strong hands‑on ASIC DFT experience with end‑to‑end ownership Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis MBIST implementation and verification; SMS experience preferred Tessent/SSN experience preferred Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows Post‑silicon debug and silicon bring‑up experience TCL, PERL, or Python scripting experience is highly preferred Skill Metrics Scan & compression (EDT) implementation LBIST implementation and verification Coverage improvements (Spyglass work) Full chip / Sub system level DFT activities. #J-18808-Ljbffr