Staff Physical Design Engineer ($300-400k pkg)

Job Description

Job Description

Staff Physical Design Engineer ($300-400k pkg)

Staff ASIC Engineer (Physical Design OR STA)

Total package up to $400k (Base up to $200k + bonus + stock)

Total first year realistic income $350-400k

Locations : San Jose, CA, Irvine, CA or Fort Collins, CO

Introduction

Are you an experienced ASIC engineer with strong expertise in physical design or STA, and a passion for working on bleeding-edge AI and high-performance silicon ? Do you enjoy diving into complex EDA reports, identifying issues early, and collaborating with top-tier engineering teams to deliver next-generation chips?

If you're excited about contributing to advanced AI/ML accelerators and infrastructure silicon , this role offers the opportunity to work at the forefront of semiconductor innovation.

Top Reasons to Work With Us

• Support customers building next-generation AI/ML, HPC, and infrastructure ASICs
• Work on cutting-edge silicon for AI workloads, including large-scale compute and accelerator architectures
• Collaborate with highly experienced cross-functional engineering teams
• Gain exposure to advanced nodes, chiplet architectures, and high-performance design methodologies
• Contribute to customer program success from early engagement through production
• Be part of a collaborative, technically strong environment

The Role / Responsibilities

As a Staff ASIC Engineer , you will work closely with senior engineers and internal teams to support customer ASIC programs focused on advanced AI and compute silicon . This is a primarily hands-on role , with opportunities to grow into broader technical ownership over time.

Your responsibilities will include:

• Assisting in the execution of customer AI/ML ASIC programs across design, test, packaging, fabrication, bring-up, and production
• Supporting customer teams with EDA tools, design flows, and methodology best practices for high-performance silicon
• Helping identify risks in quality, schedule, or dependencies and contributing to mitigation efforts
• Running physical design or STA validation flows to ensure designs meet stringent tape-out standards for advanced nodes
• Collaborating with cross-functional teams to resolve complex implementation challenges in AI and compute architectures
• Staying current with emerging AI silicon trends, IP, and implementation methodologies
• Supporting program communication across engineering and internal partner teams

Essential Skills

• Experience with multiple ASIC tape-outs (advanced nodes preferred)
• Strong understanding of PPA tradeoffs , especially in high-performance designs
• Knowledge of low power design and power management in compute-intensive systems
• Hands-on experience in physical design or STA , including relevant EDA tools and flows
• Exposure to broader ASIC flows (logic simulation, test, packaging)
• Scripting experience (TCL, shell, or similar)
• Strong communication and collaboration skills

Bonus Points For

• Experience with AI/ML accelerators, HPC, or large-scale compute SoCs
• Exposure to SERDES or high-speed interfaces
• Experience in RTL design, microarchitecture, or front-end flows
• Knowledge of DFT (scan, MBIST, repair)

Benefits

• Health, dental, and vision insurance
• Life and disability insurance 
• FSA and HSA
• 401k with match
• ESPP
• Generous PTO
• Annual bonus from 15-30% (depending on your level)
• VERY generous stocks! 

- For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. This job was first posted by CyberCoders on 07/01/2026 and applications will be accepted on an ongoing basis until the position is filled or closed. Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter .  Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at  View email address on ziprecruiter.com to make arrangements.