Senior System Integration and Validation Engineer

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first.We are hiring a Senior Engineer to lead system validation, debug, and cross-functional alignment on one of our most consequential silicon programs. Your work will sit on the critical path of every flagship build, and the judgment you bring to ambiguous, multi-team failures is the difference between shipping on milestone and slipping! The two hardest, highest-leverage problems in this seat:Find critical silicon and platform issues before they reach the customer — by shifting validation coverage left with system stress, PVT, and feature-interaction tests that catch escapes before software hardens. Your work shows up in DPPM, escape rate, and ramp confidence.Build AI-enabled validation as a real capability, not a demo — by deploying debug, triage, root-cause hypothesis generation, and regression workflows with the evals and guardrails that make them trustworthy enough to gate production decisions.What you’ll be doing:Own end-to-end system validation of NVIDIA GPU, SoC, and platform programs — feature checks, PVT stress, system-stress campaigns at scale, and multi-unit fleet testing.Lead debug of the hardest cross-stack issues — logic, signal integrity, power delivery, firmware, and software interaction — and drive them to root cause with reusable workarounds and productized fixes.Develop test plans, scripts, and automation for next-generation chips ahead of physical builds, translating architecture, boot flows, high-speed I/O, and power and thermal dependencies into executable coverage.Design and deploy AI-enabled debug and validation workflows used by the team — with explicit guardrails (evals, regression validation, false-positive handling) and measurable impact on cycle time, debug velocity, or escape rate.Translate complex silicon and system risk into decision-ready options for technical and executive audiences — without padding or hand-waving.Partner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering — including counterpart engineers in India and other major hubs.Lead crisis-mode debug task forces when a program is stuck, and convert the learnings into reusable methodology for adjacent programs.What we need to see:BTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering (or equivalent experience), plus 8+ years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products.Hands-on debug depth across silicon, board, and software boundaries — logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior — with strong EE fundamentals across SI/PI, power delivery, and thermal, and a working understanding of GPU, CPU, or SoC architecture across PC, Datacenter, or Automotive.At least one specific example of taking an ambiguous, multi-team failure to root-cause closure with a productized fix, and a track record of leading a project team end-to-end through a real crisis with decision points you owned.Demonstrated AI-driven validation workflow you built or scaled, not just used — with adoption beyond yourself and measurable impact on debug velocity, coverage, or escape rate. You can describe the guardrails you put in place and where AI is dangerous in your workflow.Ways to stand out from the crowd:A history of building reusable validation methodology, debug playbooks, or test frameworks that were adopted by other programs or teams — backed by patents, conference papers, invited talks, or recognized contributions.Hands-on subsystem depth in HBM, SerDes or high-speed I/O, power and thermal, or advanced packaging — failure modes, debug instrumentation, and the tradeoffs that show up in production.Experience partnering deeply with a counterpart team in India or another major engineering hub — examples of shared culture, shared metrics, and shared on-call across geographies.AI work that goes beyond personal-copilot use — agentic workflows, RAG-grounded debug assistants, regression bucketing, or automated triage deployed at team scope with adoption metrics.NVIDIA is the world leader in accelerated computing, and our work powers AI, gaming, robotics, autonomous systems, and scientific discovery. We invest in our people with competitive benefits, flexible time off, and continuous learning, and we build a team where everyone can do their best work. Come help us build chips that change what is possible!#LI-HybridYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until September 27, 2026.This posting is for an existing vacancy.NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa ClaraType: Full time