Staff Mixed-Signal Verification Engineer: Power ICs
Renesas
Renesas is seeking a Staff Mixed Signal Verification Engineer to advance verification of PMICs and power-management IP in Chandler, AZ. You will collaborate with design, systems, CAD, and customer teams to drive successful development and sign-off of complex mixed-signal devices. You will lead analog/mixed-signal verification using AMS and DMS methods, develop SystemVerilog RNM and Verilog-AMS models, and drive verification plans toward tapeout sign-off while mentoring others on complex silicon #J-18808-Ljbffr Renesas
Vacancy posted 9 hours ago
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