Signal Integrity Engineer
$100kTenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a Signal Integrity Engineer to join our growing team. The ideal candidate will have a wealth of exposure designing high speed interconnects, breakout design, material trade-offs and verification. A background in electrical engineering, electronics or relevant fields is required. Must love all things high speed! This role is hybrid, based out of Santa Clara, CA or Austin, TX or Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have a Bachelor’s degree in Electrical Engineering (or equivalent) and 5+ years working in high-speed digital design with a focus in high-speed PCB or package design at 10Gbps and above (e.g. 100GbE, GDDR6, PCIe Gen5+). You’re comfortable working with high-speed performance metrics such as ICR, ERL, COM, NEXT, and FEXT as well as knowledge of high-speed connector technologies, including NPO, CPO, and emerging standards. You are proficient with PCB ECAD tools (ideally Cadence Allegro). You communicate clearly (written and verbal), think critically, and love solving complex signal integrity problems. You’re enthusiastic about all things high speed and enjoy collaborating across teams What We Need Design, extract, and simulate complex breakout structures, including end-to-end simulations and validation against physical hardware. Perform simulation and extraction of board models for both SI and PI. Contribute to design and sign-off with internal and external ASIC packaging teams, ODMs, and internal layout teams. Create design specifications, work with external vendors, and drive adoption of new interconnect and packaging technologies. Actively participate in design reviews, providing insight from your SI/PI expertise and a broader system perspective. Support post-silicon bring-up and help troubleshoot production and field failures related to signal and power integrity. Document design processes and provide training/knowledge sharing to other team members. What You Will Learn How to work at the cutting edge of high-speed interconnects, influencing the next generation of ASIC packaging and PCB architectures. Deep exposure to advanced ASIC packaging flows and collaboration models with internal and external packaging teams. Hands-on experience with emerging high-speed connector technologies and materials, including evaluating material trade-offs for performance and manufacturability. Best practices for end-to-end SI/PI validation, from simulation through to lab correlation, post-silicon bring-up, and field failure analysis. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded. #J-18808-Ljbffr Tenstorrent
$200k - $351k
Celestica is seeking a highly motivated Signal Integrity Engineer to design and build market-leading Hardware Platform Solutions in California. This position requires expertise in digital PCB designs, lab verification, and troubleshooting signal integrity issues. The ideal...Suggested- Sr. H/W Design Engineer/Signal Integrity Terms: Contract/Potential Perm Location: Hybrid: San Diego, Ca Start Date: ASAP Experience designing complex digital boards with higher end SoC type FPGAs Altera, Xilinx, MicroSemi Experience with high speed signals and devices...SuggestedPermanent employmentContract workImmediate start
- Langham Recruitment is hiring a Senior Signal Integrity Engineer in California, United States. In this role, you will lead the design, modelling, and validation of high-speed optical link platforms for AI data centre interconnects, ensuring end-to-end signal integrity....Suggested
$100k
A leading technology company is seeking a Signal Integrity Engineer to design and simulate high-speed interconnects. This hybrid role requires a Bachelor’s in Electrical Engineering, with 5+ years of relevant experience in high-speed digital design. The ideal candidate...Suggested- Job Description Position Summary The Optical/Signal Integrity (SI) Engineer reports to the Principal Photonic Signal Integrity Engineer (APC MWIS WG Chair) and is responsible for the testing of high-speed optical connectors to validate their signal integrity. The Optical...SuggestedWork experience placement
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