Physical Design Engineer

We are seeking an experienced and highly skilled Chip-Level / SoC-Level Design Engineer to join our innovative team. The ideal candidate will excel in RTL-to-GDSII design processes across both block-level and top-level integration, demonstrating expertise in advanced implementation tools and techniques. This role offers the opportunity to work on cutting-edge designs for lower nodes (3nm, 4nm, 5nm) and contribute to full-chip and SoC-top projects.

Key Responsibilities

• Perform block-level and chip-level design from RTL-to-GDSII.
• Handle synthesis, floor-planning, place & route, timing/EMIR/PV closure, and signoff at both block and SoC-top levels.
• Utilize the Synopsys Implementation tool suite (Fusion Compiler, ICC2).
• Implement controllers for High-Speed IO IPs and integrate them at SoC-level.
• Conduct structural implementation, including datapaths, bus planning, and routing across chip-level hierarchies.
• Design with multi-power domains and ensure proper integration at SoC-top.
• Develop and maintain scripts using TCL and Python to support automation at block and chip-level.

Requirements

• Proficiency with Synopsys Implementation tool suite (Fusion Compiler, ICC2).
• Experience in structural implementation of datapaths, bus planning, and routing at block and chip-level .
• Strong scripting skills in TCL and Python.
• Familiarity with multi-power domain design and SoC-top integration.
• Experience with controllers for High-Speed IO IPs and their chip-level integration.
• Knowledge of lower-node technologies (3nm, 4nm, 5nm) is a strong advantage.