RTL Design Intern — Verilog/ML Hardware, 12‑week Paid
Etched.ai, Inc.
Etched.ai, Inc. is seeking an RTL Intern in San Jose, CA to design microarchitecture and implement logic in verilog. You'll work on modern machine learning architectures and contribute to RTL development. This 12-week paid internship includes housing support and meals. Ideal candidates are pursuing degrees in electrical or computer engineering and have some familiarity with digital logic, SystemVerilog, or Python. Mentorship from top engineers is also provided. #J-18808-Ljbffr Etched.ai, Inc.
Vacancy posted more than 2 months ago
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