Principal Product Development Engineer

NVIDIA seeks a Principal Sr. Product Development Engineer with transformative leadership skills to serve as the technical anchor for the Mixed‑Signal Product Development team in our central Product Development Engineering Organization. In this key leadership position, you will build the technical roadmap and processes that enable next‑generation, deep‑submicron CMOS mixed‑signal technologies to progress from design validation into manufacturing ramp and mass production. You will serve as the main technical link between System Level Testing, test engineering, reliability, and manufacturing teams. Your role includes driving yield architecture, test optimization plans, and product performance validation for innovative mixed‑signal solutions used in AI, networking, and high‑performance computing systems. The ideal candidate has deep technical expertise in advanced CMOS nodes and high‑speed mixed‑signal systems. They also have a strong history of guiding complex product development lifecycles in high‑volume semiconductor manufacturing. What You'll Be Doing Cross‑functional leader to bridge design requirements to manufacturing solutions Drive the end‑to‑end technical product development strategy from early silicon validation through qualification and high‑volume manufacturing. Define, develop, and implement advanced validation methodologies and innovative test strategies for deep‑submicron analog and mixed‑signal silicon builds. Work in close partnership with Analog/Digital Development, System Level Testing, groups dedicated to product validation, durability, and production. Influence strategies for design‑for‑test (DFT), design‑for‑manufacturability (DFM), and built‑in self‑test (BIST). Maintain consistent alignment from architectural codesign through to mass production. Coordinate and architect complex parametric, electrical, and mixed‑signal characterization frameworks for high‑speed interfaces, power management units, and clocking circuits. Lead deep‑divided root‑cause analysis and resolve highly complex technical anomalies related to silicon performance, Vmin/Fmax charting, yield excursions, and product reliability. Architect yield improvement initiatives, test time reduction strategies, and manufacturing efficiency improvements across wafer‑sort and final packaged test flows. Provide structured, data‑driven feedback to analyze silicon performance, design margins, process corners, and parametric sensitivities to improve future architectures. Establish scalable data analysis frameworks, automated data pipelines, and statistical methodologies for high‑volume validation and production monitoring. What We Need to See Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience. More than 12 years of background in semiconductor product development, validation, or manufacturing engineering. 12+ years of experience serving as a technical lead, principal engineer, or guiding cross‑functional technical teams through product lifecycles. Extensive technical knowledge of advanced CMOS process technologies, analog/mixed‑signal circuit behavior, and digital logic interaction. Proven experience in yield analysis, product characterization, and applying statistical data analysis tools (e.g., JMP, Spotfire) for engineering insights and data‑driven yield improvements. Automation: High proficiency in automation and scripting (e.g., Python, MATLAB) for validation, data analysis, and test infrastructure. Proven capability to overcome significant cross‑functional obstacles and lead problem‑solving within tight delivery timelines. Ways to Stand Out From the Crowd Extensive technical knowledge in foundry device physics and working closely with foundries to identify and address process anomalies and guide fab engineering teams to overcome major yield challenges. Deep expertise in defining ATE flows, structural and functional test pattern conversion, and handling high‑power FinFET or gate‑all‑around (GAA) silicon. Background in multi‑chip modules (MCM), 2.5D/3D packaging integration, or CoWoS technologies. Proven success leading silicon product ramps from low‑yielding prototype phases to stable, high‑volume manufacturing scale. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 240,000 USD - 379,500 USD. You will also be eligible for equity and benefits. #J-18808-Ljbffr NVIDIA Gruppe