Staff Design Verification Engineer for AI Chip

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

Key Responsibilities

• Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon.

• Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture.

• Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage.

• Implement tests, manage regressions, gather coverage, and debug test failures.

• Collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation.

• Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.

• Continuously enhances verification infrastructure and flows to improve efficiency and quality.

• Contribute to the evolution of the overall verification methodology and best practices across the organization.

Skills and Qualifications

• Great debugging and problem-solving skills.

• Deep knowledge of SystemVerilog testbench, DPI and UVM.

• Excellent programming skills and knowledge of software engineering practices including object-oriented design.

• Experience developing scalable and portable testbenches and components.

• Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate level simulations.

• Proficient in scripting languages such as Python or Perl.

• Good interpersonal skills and the ability to work as a standout colleague are a must.

• Extremely self-motivated and eager to solve problems

• 10+ years of Design Verification experience.

Desired Skills and Qualifications

• Knowledge of pipelined processor architecture.

• BS or MS in Computer Science or Electrical Engineering.

• 10+ years of hands-on Design Verification experience.

Location : Sunnyvale, CA

The base salary range for this position is $225,000 to $270,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Why Join Cerebras

People who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

1. Build a breakthrough AI platform beyond the constraints of the GPU.

2. Publish and open source their cutting-edge AI research.

3. Work on one of the fastest AI supercomputers in the world.

4. Enjoy job stability with startup vitality.

5. Our simple, non-corporate work culture that respects individual beliefs.

Find out more about what it's like to work at Cerebras here !

Apply today and become part of the forefront of groundbreaking advancements in AI!

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

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