DFT Architect

Job Details:

Job Description:

About Altera

At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

The Altera DFT team is seeking an experienced and highly technical DFT Architect to lead the definition, strategy, and execution of next-generation Design-for-Test solutions across complex SoC and FPGA platforms. This is a high-impact technical leadership role within an industry-leading IC design organization focused on advanced technologies including FPGA, AI acceleration, processors, DSP, SERDES, high-speed IO, chiplet-based architectures, and 2.5D/3D multi-die packaging solutions.

As a DFT Architect, you will drive end-to-end DFT architecture and methodology development across large-scale, highly integrated silicon programs. You will define scalable DFT strategies spanning scan architecture, compression, MBIST/LBIST, hierarchical DFT, IJTAG/IEEE standards, silicon debug, and production test optimization. You will partner closely with architecture, design, validation, physical design, product engineering, and manufacturing teams to ensure robust testability, manufacturability, and high-quality silicon delivery.

This role requires deep expertise in modern DFT implementation, strong architectural leadership, and the ability to influence technical direction across multiple product generations and cross-functional engineering organizations.

Responsibilities:

• Define and own DFT architecture strategy for complex FPGA, SoC, processor, DSP, SERDES, IO, and multi-die/chiplet-based products.
  
• Lead the development of scalable DFT methodologies and implementation flows across RTL, gate-level, and hierarchical integration environments.
  
• Architect advanced scan, compression, ATPG, MBIST, LBIST, boundary scan, and in-system test solutions to achieve aggressive coverage, quality, and cost targets.
  
• Drive DFT planning and integration for advanced packaging technologies including 2.5D/3D ICs and heterogeneous multi-die systems.
  
• Collaborate with architecture, RTL, physical design, timing, validation, and product engineering teams to ensure seamless DFT integration throughout the design lifecycle.
  
• Establish and enforce DFT design guidelines, test specifications, timing constraints, and signoff criteria across large engineering programs.
  
• Lead root-cause analysis and debug efforts for pre-silicon and post-silicon test failures, yield issues, and manufacturing escapes.
  
• Optimize manufacturing test strategies for coverage, test time, yield improvement, power-aware test, and overall production efficiency.
  
• Drive adoption of next-generation DFT technologies, automation, and best practices to improve productivity, scalability, and quality.
  
• Mentor and provide technical leadership to DFT engineers across multiple projects and initiatives.
  
• Partner with EDA vendors and internal methodology teams to evaluate and deploy advanced DFT tool capabilities and flows.
  

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$187,000 - $270,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

#LI-MD1

Qualifications:

Minimum Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 10+ years of industry experience in the following - OR - Master's degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of industry experience in the following:

• Experience in full chip DFT Architecture for complex designs.
  
  
• Experience in DFT design and verification at both RTL and gate level.
  
• Experience in EDA tools such as synthesis and scan insertion tools, ATPG tools, simulation and debug tools, STA tools
  
• Design automation experience and proficiency in scripting languages such as Perl/TCL
  

Preferred Qualifications:

• Experience with SSN, test compression, BIST (MBIST/LBIST), and advanced fault models.
  
• Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT.
  

Job Type:
Regular

Shift:
Shift 1 (United States of America)

Primary Location:
San Jose, California, United States

Additional Locations:

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.