Verification Engineer: Automated HDL Validation
IMC
IMC is seeking a Verification Engineer to join its R&D team in Chicago. You will verify complex hardware designs using UVM, collaborate with RTL and SW teams, and automate verification flows for rapid development. The role requires experience with SystemVerilog/Verilog, C++, scripting, and Linux, plus familiarity with 3rd party EDA tools. The position offers a competitive base salary, discretionary bonus eligibility, and benefits including paid leave and insurance. #J-18808-Ljbffr IMC
Vacancy posted 5 days ago
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