Senior Analog/Mixed-Signal Verilog Modeling Engineer
$120k - $192kBroadcom Corporation
Broadcom Inc. is looking for an experienced engineer to develop Digital-Mixed Signal (DMS) models for various analog IPs. The ideal candidate will have over 8 years of experience and be proficient in SystemVerilog and Verilog-AMS. This role involves collaborating with design and DV teams and requires strong scripting skills in TCL, Perl, and Python. Compensation includes a competitive salary range of $120,000 to $192,000, along with comprehensive benefits such as medical plans and 401(k) matching. #J-18808-Ljbffr
Vacancy posted 8 hours ago
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