Fpga Design Engineer

Job Title FPGA Design Engineer Location Rolling Meadows, IL Security Clearance Active Secret clearance required. Job Type Permanent Responsibilities Design, develop, and implement FPGA-based digital logic for advanced defense systems. Create and optimize VHDL code for high‑performance, real‑time applications. Collaborate with cross‑functional engineering teams, including RF, systems, hardware, and firmware. Participate in integration, testing, and troubleshooting of FPGA designs in lab environments. Document design specifications, test procedures, and technical reports. Ensure compliance with defense‑industry standards, security requirements, and program objectives. Essential Skills Full‑lifecycle FPGA design and development experience. Expertise in VHDL. Proficiency with Xilinx, Intel, or Altera FPGA toolchains. Strong digital logic fundamentals and hardware debugging skills. Ability to work in a classified environment with an active Secret clearance. Additional Skills & Qualifications Experience in Aerospace & Defense, SATCOM, Infrared systems, or RF‑based technologies. Familiarity with high‑speed interfaces, DSP blocks, or embedded processing. Understanding of system‑level integration in EW or RF systems. Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 3–8 years of FPGA design experience. Benefits Medical, dental & vision Critical illness, accident, and hospital coverage 401(k) retirement plan – pre‑tax and Roth post‑tax contributions available Life insurance (voluntary life & ADDS for the employee and dependents) Short‑ and long‑term disability Health Spending Account (HSA) Transportation benefits Employee Assistance Program Time off / leave (PTO, vacation or sick leave) Pay $55.00 – $80.00 per hour Application Deadline June 24, 2026 Equal‑Opportunity Statement The company is an equal‑opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law. To request a reasonable accommodation, please email View email address on click.appcast.io. San Francisco Fair Chance Ordinance: For all positions located in the city and county of San Francisco, the employer will consider qualified applicants with arrest and conviction records. #J-18808-Ljbffr Actalent