Senior Photonics Design Engineer, Actives Design

Job Details Job Description Intel Integrated Photonics Solutions (IPS) is at the forefront of silicon photonics integration and commercialization. Since announcing the world’s first hybrid silicon laser nearly a decade ago, our team continues to lead the industry with cutting‑edge technology and efficient, scalable high‑volume manufacturing. Our dedication to advanced development ensures that Intel Silicon Photonics continues to drive future data center and AI datacenter bandwidth growth with smaller form factors, co‑packaging solutions, and higher speeds from 400G to 1.6T+ and beyond. We are seeking exceptional talent to accelerate this transformative journey. If you’re passionate about shaping the future of photonics technology, we want to hear from you. Position Overview Intel’s IPS is seeking a Senior Photonics Design Engineer specializing in active components and high‑speed design. This role requires extensive experience in photonic integrated circuit (PIC) development and a proven track record of design innovation. You will be instrumental in advancing Intel’s silicon photonics platform and driving next‑generation optical communication solutions. Key Responsibilities Component Design and Architecture: Design, simulate, and develop photonic components (modulators, high‑speed detectors, phase control, carrier injection, diodes) and influence PIC architecture decisions. Design Optimization: Perform tolerance analysis and optimize components for performance, power, area, and reliability using advanced modeling techniques. Test Chip Leadership: Drive end‑to‑end test chip execution including design, layout coordination, tape‑out, and validation. Data Analysis and Improvement: Analyze characterization data to identify performance gaps and implement data‑driven design improvements. Innovation and Methodology: Develop photonic modeling methodologies and propose new test approaches to accelerate development cycles. Research and IP Development: Conduct research in novel photonic technologies, define next‑generation architectures, and drive IP development programs. Qualifications Minimum Qualifications: PhD in Electrical Engineering, Physics, or a similar discipline with 4+ years of experience in a related field and 4+ years of relevant industry experience. Extensive (6+) years of designing, simulating, and testing silicon photonic design experience in industry or research environment. High‑Speed Design: Designing, simulating, and testing high‑speed optical modulators and/or detectors for 50+ Gbaud applications in silicon or III‑V platforms. Design and Simulation Tools: Proficiency with optical/RF design and simulation tools such as Sentaurus, Silvaco, Lumerical DEVICE, HFSS, ADS, Lumerical FDTD/MODE, Lumerical Interconnect, RSoft, Tidy3D, Harold‑Photon Design. Test and Characterization: Hands‑on experience with standard photonic test methodologies and equipment including optical spectrum analyzers, tunable lasers, optical backscatter reflectometers, optical vector analyzers, and fiber/free‑space coupling systems. Data Analysis: Expertise in PIC test data analysis and design optimization using statistical analysis tools (JMP) or statistical libraries in MATLAB/Python. Layout Tools: Familiarity with industry‑standard layout tools such as Cadence and KLayout. Preferred Qualifications: Specialized Modulator Experience: Silicon photonic microring modulator design expertise, especially with MRM modulators or advanced materials such as BTO, TFLN, III/V. Electronic Integration: Understanding of high‑speed electronic ICs including modulator drivers, linear and limiting TIAs, post‑amplifiers, FFE/DFE filters, and DSPs. Control Systems: Experience developing optical modulator bias control systems. System‑Level Modeling: Experience with comprehensive optical link modeling and system‑level performance optimization. Experience with 100G+ high‑speed photonic components. Familiarity with foundry processes (AIM Photonics, GlobalFoundries, TSMC, etc.). Publications in peer‑reviewed photonics journals. Customer‑facing or product development experience. Experience with active component design for bias control such as heaters, carrier injection devices, and passive silicon photonic devices. Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location US, California, Santa Clara Business group At the Data Center Group (DCG), we’re committed to delivering exceptional products and delighting our customers. We offer both broad‑market Xeon‑based solutions and custom x86‑based products, ensuring tailored innovation for diverse needs across general‑purpose compute, web services, HPC, and AI‑accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload‑driven leadership products and close collaboration with our partners. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. #J-18808-Ljbffr Dormont Manufacturing Co