Validation Engineer 3

Job Description

Job Description

Validation Engineer 3
SAN JOSE, CA
12 months contract

Description: Overview:
We are seeking a senior-level contractor to lead production test development for SoC devices integrating copackaged optics (CPO) SerDes interfaces. This role centers on ATE program development, DFT/BIST enablement, yield/quality optimization, and high-volume manufacturability. Strong understanding of SerDes and protocols such as UCIe and PCIe is required, with emphasis on translating characterization into robust, multisite production tests. Experience with Python-based automation and data analytics is essential; familiarity with AI-assisted tools for test development and data triage is a plus.

Key Responsibilities:
" Own development, integration, and maintenance of wafer sort and final test programs on ATE for SoC SerDes with copackaged optics
"Define and implement production test coverage for SerDes PHY and protocol features (PRBS, loopback, margining, FEC, CDR lock, EQ settings) using on-die BIST/DFT and ATE instrumentation
"Implement and optimize multisite strategies, parallel test execution, guardbanding, and test time reduction while meeting quality and coverage goals
"Correlate bench/char results to ATE: develop golden-unit flows, establish limits, build characterization-to-production handoff, and close gaps
"Integrate DFT features (scan/ATPG, boundary scan, MBIST/LBIST, JTAG) into production flows; manage pattern conversion, timing sets, and pin maps
"Implement UCIe/PCIe-related production checks: link training emulation, LTSSM state verification via firmware or test hooks, compliance counters, and error injection/monitoring
"Build Python-based tooling for ATE control, data parsing, STDF analytics, dashboards, and automated limit updates; integrate with MES/SPC and CI pipelines
"Collaborate with silicon design, firmware, DFT, product engineering, OSAT/probe, and SI teams to resolve issues and qualify ECOs/revisions
"Document test plans, specifications, vector maps, limits, and release notes; train operations teams and support sustaining engineering
Required Qualifications:
" Hands-on experience developing on leading ATE platforms (e.g., Advantest V93K/AC , Teradyne UltraFLEX/UltraFLEXplus) including timing sets, DC/AC measurements, and multisite
"Strong understanding of SerDes/PHY fundamentals: equalization, CDR, CTLE/DFE, PRBS/BER, margining, jitter/eye constraints, and on-die BIST integration
"Proficiency in Python for automation and data analytics; experience with STDF parsing, visualization, and automated SPC/anomaly detection
"Solid DFT background: scan/ATPG patterns, boundary scan, MBIST/LBIST, JTAG access, pattern formats (WGL/STIL), and pattern bring-up on ATE
"Working knowledge of UCIe and PCIe (Gen5/Gen6 preferred) from a production test perspective: link checks via firmware/test hooks, error counters, and compliance indicators
"Excellent documentation, cross-functional communication, and problem-solving skills