Senior ASIC Timing Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a NVIDIA employee, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. What You’ll Be Doing Drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, chiplet level, and/or full chip level. Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets. Help drive frontend and backend implementation from RTL to GDSII, including synthesis, equivalence checking, floor‑planning, timing constraints, timing and power convergence, and ECO implementation. What We Need To See A great teammate. BS (or equivalent experience) in Electrical or Computer Engineering with 8 years experience, or MS with 4+ years experience in synthesis and timing. Hands‑on experience in full‑chip/sub‑chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence. Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis. Expertise in physical design and optimization (e.g., placement, routing, cell sizing, buffering, logic restructuring, etc.) to improve timing and power, along with a background in implementing them through ECOs. Background in logic synthesis and/or logical equivalence checking (LEC). Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus). Proficiency in Python, Tcl and Make for automation and scripting tasks. Ways to Stand Out From the Crowd Background in domain specific STA and timing convergence, such as CPUs, GPUs or network processor implementation or SOCs. Understanding of DFT logic and experience with DFT timing closure for various modes (e.g., scan shift and capture, transition faults, BIST). Knowledge of deep sub‑micron technology and associated process variation effects, including modeling and converging while considering process variations. Experience in methodology and/or flow development as well as automation. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $168,000 – $264,500 for Level 4, and $196,000 – $310,500 for Level 5. You will also be eligible for equity and benefits. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr NVIDIA AI