Engineer, Senior|6121 Engineer, Senior|6121

Top 5 Required Skills Silicon debug on Bench platform for test and characterization of industry standard SerDes Interfaces like Ethernet/PCIe/USB4/USB3/UFS/MIPI. SerDes is a must. Familiarity with SERDES Transmitter and Receiver design blocks, High Speed Analog/Digital Circuits, VLSI, semiconductor physics. Familiarity with concepts in Power Integrity, Signal Integrity, Jitter Analysis, equalization techniques (CTLE/DFE). Hands on experience with lab equipment such as Oscilloscopes, J-BERT, TDRs, VNAs. Familiarity with Board Design concepts (Schematic reviews, Layout best practices, etc). Technologies Experience with Python/C# for test automation. Strong interpersonal, problem solving & Silicon debugging skills. Required Education 5+ years experience with a Bachelor's degree in Computer Science, Engineering, Information Systems. -OR- 3+ years experience with a Master's degree in Computer Science, Engineering, Information Systems. Physical Requirements None. Key Words SerDes Test Silicon Debug HSIO Char PCIe Test USB Test Compliance Test Silicon Characterization Job Description This position is for the Post Silicon Test and characterization of highly integrated SOCs (System on Chip) designed by Qualcomm. The preferred candidate would be someone with experience in SERDES test and characterization on the bench platform. The main responsibilities include developing test and debugging silicon to characterize High Speed SERDES Interfaces such as Ethernet, PCIe, USB3, UFS, DP, MIPI (DSI, CSI), PLLs and leading‑edge LP‑DDR & PC‑DDR Subsystem components (DRAM, DRAM Controller, PHY, IOs, Clocking architecture, Delay circuits, Power Distribution Network) as well as other proprietary interfaces. Responsibilities include developing and executing characterization plans for High Speed Serial interfaces, optimizing analog front‑end parameters, compliance testing and validation, supporting first silicon bring‑up & debug. You will also assist in HW design and debug power integrity (PI) and signal integrity (SI) issues related to package and board design. You will work closely with the design team for chip/circuit bring‑up and debugging, and with Application Engineering teams to resolve customer issues/RMA debug in a time‑critical environment. Work Location San Diego Lab AQ-254, in the lab presence required all five days initially and at least 3 days a week after getting fully acquainted with hardware and software setup of the lab. Shift Regular daytime office hours. #J-18808-Ljbffr ALTEN