Accelerator Driver / Firmware Interface Lead

About Velaura Velaura is building the next generation of compute platforms for Physical AI. As AI moves beyond the datacenter into robots, autonomous mobile systems, drones, and other embodied systems, traditional compute architectures are increasingly constrained by power, memory bandwidth, latency, real‑time requirements, and functional safety considerations. Our mission is to develop the foundational compute technologies that enable intelligent systems to operate efficiently in the physical world. We are assembling a team of exceptional architects and engineers to rethink how AI, sensing, memory, and control interact within a modern computing platform. Role Overview We are looking for an Accelerator Driver / Firmware Interface Lead to own the low‑level software boundary between Velaura’s AI accelerator hardware, firmware, Linux kernel driver, and user‑space runtime. This role will lead development of the NPU kernel driver, firmware ABI, command submission model, interrupts, scheduling primitives, firmware loading, reset/recovery, telemetry, debug interfaces, and low‑level validation. The ideal candidate has deep experience with Linux device drivers, accelerator firmware interfaces, DMA/IOMMU, and complex hardware/software bring‑up. Responsibilities Lead architecture and development of the NPU kernel driver and firmware interface. Own command submission, queues, interrupts, synchronization, memory mapping, scheduling primitives, firmware loading, telemetry, and error handling. Define the firmware ABI and versioning strategy between NPU firmware, kernel driver, runtime, compiler‑generated artifacts, and diagnostic tools. Work with hardware and firmware teams on registers, command streams, error states, reset behavior, performance counters, debug hooks, and silicon errata. Partner with Kernel Memory/DMA/IOMMU and Runtime teams on buffer sharing, dma‑buf, IOMMU mappings, cache coherency, and zero‑copy execution. Define reset/recovery, hang detection, multi‑process/multi‑context behavior, device isolation, and robustness requirements. Support pre‑silicon driver development using simulation, emulation, FPGA, or virtual‑platform environments. Establish driver validation, firmware ABI tests, stress tests, fault‑injection tests, and first‑silicon bring‑up diagnostics. Evaluate upstream Linux accelerator‑driver strategy where appropriate. Hire, mentor, and lead engineers focused on NPU driver, firmware interface, and low‑level accelerator software. Required Qualifications Deep Linux kernel driver development experience for complex devices such as GPUs, NPUs, DSPs, networking ASICs, storage, cameras, or other accelerators. Strong understanding of DMA, IOMMU/SMMU, interrupts, MMIO, command queues, firmware loading, synchronization, and hardware error handling. Strong C programming skills and ability to debug hardware/software interactions at the register, firmware, kernel, and user‑space levels. Experience defining or maintaining firmware ABIs, driver interfaces, ioctl or sysfs/debugfs interfaces, telemetry, and diagnostic hooks. Experience with lab bring‑up, pre‑silicon environments, first silicon, or hardware validation workflows. Ability to work across hardware architecture, firmware, runtime, compiler, Platform SW, SQA, and performance teams. Strong debugging skills using UART, JTAG, kernel tracing, firmware logs, hardware counters, or equivalent tools. Preferred Qualifications Experience with AI accelerators, GPU drivers, DRM/accel subsystem, DSP drivers, or heterogeneous compute platforms. Experience with dma‑buf, dma‑fence, DRM, IOMMU, virtualization, multi‑process scheduling, or device isolation. Experience with firmware crash capture, device reset/recovery, hang detection, and fault injection. Experience upstreaming Linux drivers or designing upstream‑quality kernel interfaces. Familiarity with AI inference runtimes, compiler artifacts, tensor memory layouts, or model execution pipelines. Experience with safety, security, or reliability requirements for embedded, automotive, robotics, or industrial systems. Compensation & Benefits At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance‑based incentives, and equity participation, allowing team members to share in the company’s long‑term success. The base pay range for this role is between $200k and $500k, and your base pay will depend on your skills, qualifications, experience, and location. In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage, paid time off, flexible work arrangements, professional development opportunities, and other benefits designed to support the well‑being and growth of our team. Velaura is committed to pay equity and transparency, and we regularly benchmark compensation to ensure we remain competitive in the market. Why Velaura? This is an opportunity to help build a new class of computing architecture at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders and architects who have delivered industry‑defining products across mobile, cloud, and AI platforms. If you enjoy building hardware, tackling difficult technical challenges, and helping shape the future of Physical AI, we would love to hear from you. #J-18808-Ljbffr