Lead Digital ASIC Architect: Mixed-Signal & Clocking IP
Jobtailor
Jobtailor is seeking an experienced digital ASIC designer to own architectural definition, RTL implementation, and system‑level integration of clocking IPs. You will design complex digital control loops, DVFS controllers, and state machines for adaptive calibration, coordinating with analog, verification, and physical design teams. The role requires deep SystemVerilog RTL expertise, 8+ years in digital ASIC design, and proven tapeout success on advanced nodes (N5/N3P+). #J-18808-Ljbffr Jobtailor
Vacancy posted 5 days ago
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