Senior Performance Modeling Architect

Gain deeper exposure to the full CPU architecture and development process, from early architectural exploration through implementation and silicon Expand your ability to connect performance models and workload behavior to real hardware design decisions Work across CPU architecture, software, compilers, and system teams to understand performance from multiple perspectives Develop new approaches to modeling, workload analysis, and architectural exploration as processor designs become increasingly complex Help shape the performance characteristics and architectural direction of future generations of Tenstorrent CPUs You can move between high-level architectural questions and detailed analysis of CPU pipelines, memory systems, workloads, and bottlenecksYou have a strong understanding of modern processor architecture and enjoy digging into why a CPU performs the way it doesYou are comfortable combining hardware architecture, software, data, and analytical modeling to solve complex performance problemsA strong collaborator and technical communicator who can turn complex modeling results into clear recommendations and drive decisions across engineering teamsA CPU architect, performance architect, or performance modeling engineer with experience influencing CPU architecture or microarchitecture decisions8+ years of experience in CPU architecture, performance modeling, microarchitecture, performance analysis, or a closely related fieldStrong analytical, problem-solving, and communication skills, with the ability to work effectively across architecture, hardware, and software teamsDemonstrated experience using performance models, simulation, or quantitative analysis to guide real architectural decisionsStrong programming skills in C++, Python, or similar languages, with experience developing or extending modeling and analysis toolsStrong understanding of CPU architecture and microarchitecture, including areas such as pipelines, execution, scheduling, branch prediction, caches, memory hierarchy, and data movement #J-18808-Ljbffr Tenstorrent