Senior SoC/ASIC Verification Architect
Prodapt
Prodapt is seeking a Senior Design Verification engineer to work onsite in Sunnyvale, CA. The role involves developing verification plans, maintaining verification environments, and collaborating with design engineers to ensure high-quality deliverables. Applicants should have 10+ years of experience in Design Verification, strong skills in Verilog/SystemVerilog, and proficiency in scripting languages such as Python. A Bachelor's or Master's degree in a relevant field is required. #J-18808-Ljbffr Prodapt
Vacancy posted 1 day ago
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