Physical Design Engineer - Static Timing Analysis

HCLTech is looking for a highly talented and self-motivated Physical Design Engineer - Static Timing Analysis to join it in advancing the technological world through innovation and creativity. Job Title: Physical Design Engineer - Static Timing Analysis Job ID: 155222 Position Type: Full Time Location: Remote We are looking for an experienced STA Engineer with strong expertise in Static Timing Analysis, timing closure, PrimeTime, SDC, MMMC, SI/OCV analysis, variation modeling, and timing ECOs across block and full-chip designs. Key Responsibilities Perform Static Timing Analysis (STA) and timing signoff for block and full-chip designs. Drive setup and hold timing closure. Develop, validate, and debug SDC timing constraints. Configure and analyze Multi-Mode Multi-Corner (MMMC) timing scenarios. Perform timing analysis using Synopsys PrimeTime (PT), PrimeTime SI (PT-SI), and Path-Based Analysis (PBA). Perform Signal Integrity, crosstalk, noise, and OCV analysis. Work with variation modeling methodologies including AOCV and POCV. Generate, analyze, and validate timing ECOs. Analyze clock architectures, clock relationships, and cross-domain timing paths. Perform block-level and full-chip timing analysis and closure. Identify timing violations and work with Physical Design and RTL teams toward closure. Support timing signoff and tape-out readiness. Develop automation and scripts using TCL and Python for STA, reporting, and debugging. Required Skills Strong hands-on experience in Static Timing Analysis (STA) and timing signoff. Strong expertise with Synopsys PrimeTime, PT-SI, and PBA. Strong experience in setup/hold analysis and timing closure. Deep understanding of SDC constraints, including development, validation, and debugging. Experience with MMMC scenario management and variation modeling. Knowledge of clock architecture and cross-domain timing analysis. Experience with Signal Integrity, crosstalk, noise, and OCV analysis. Strong understanding of AOCV and POCV. Experience with timing ECO generation and validation. Strong scripting skills using TCL and Python. Experience with block-level and full-chip STA. Experience supporting timing signoff and tape-out. Pay and Benefits Pay Range Minimum: $95000/Year Pay Range Maximum: $192000/Year HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to for investigation. A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year How You’ll Grow At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best.