Principal/Senior Staff Physical Design Engineer (Full-chip/SoC)

Job Description

As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions.

Location: San Diego or San Jose, CA

Responsibilities

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• Complete entire physical implementation of the block and chip level
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• Perform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV.
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• Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs
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• Analyze the quality of the floorplan and Customized Clock tree structure and Place & Route
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• Implement ECOs for timing closure
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• Signal EM/Noise and Power IR/EM analysis and fix
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• DRC/LVS/ERC/ANTENNA analysis and clean up
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• Timing verification and sign-off
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• Physical verification and sign-off
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Minimum Qualifications

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• Master’s degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor’s degree in electrical/computer science engineering plus 15+ years of industry experience
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• Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
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• The entire SOC implementation and verification flow from RTL-to-GDS that includes fullchip floorplan, place and route, CTS, and layout verification signoff on lower power SoC
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• Netlist (or RTL)-GDS physical implementation experience
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• In depth knowledge of major EDA tools/design flows
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• Strong Cadence experience/background
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• Experience with TSMC N22 or below technology
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• Experience in chip integration and signoff
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• Experience in Perl/TCL language programming
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Preferred Qualifications

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• Strong experience in Low-power implementation methodology
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• Strong experience in Advanced timing signoff methodology
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• Knowledge of DFT (BSCAN, MBIST, SCAN) and understanding of their impact on physical design flows
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• Able to independently complete Netlist-GDS P&R, signoff task
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• Proven record in multi-million gate design production tapeouts
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