Low-Power SoC Architect for HBM & AI Workloads

Micron Technology, Inc is seeking a Lead Low Power Architect to define SoC-level power architecture for next‑gen HBM logic dies and memory‑centric SoCs. You will model power and performance and collaborate across RTL, verification, and physical design to implement power intent. The role requires deep expertise in DVFS, clock gating, and UPF/CPF, and requires strong cross‑functional communication. Master’s or PhD in a relevant field is preferred; 10+ years of experience is typical. #J-18808-Ljbffr Micron Technology, Inc