Staff DV Engineer: Coherent Interconnect & SoC (Equity)
Sifive
Sifive in Boston is seeking a Staff Design Verification Engineer to drive the verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs. The ideal candidate should have over 7 years of ASIC or SoC design verification experience, strong skills in SystemVerilog, and an understanding of protocol correctness. You will own complex verification tasks, develop robust environments, and collaborate closely with architecture and design teams to ensure quality and efficiency in the project. #J-18808-Ljbffr Sifive
Vacancy posted 5 days ago
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