Senior FPGA Architect (Compute Test, North Reading)

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Senior FPGA Architect (Compute Test, North Reading)

Date: Sep 24, 2026

Location: North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

Teradyne's Compute Test Division develops advanced test solutions for next-generation silicon, including high-performance SoCs and accelerators powering modern compute and AI systems. We are seeking a Senior FPGA Architect to architect and deliver high-performance FPGA-based solutions at the heart of our test platforms. This role works at the intersection of FPGA design, board-level hardware, and system architecture to solve complex challenges involving high-speed interfaces, large digital systems, tight timing margins, and system-level constraints. Based on site in North Reading, Massachusetts, the position is expected to work in the office three days per week and collaborate across functions to deliver robust, scalable solutions that directly affect the quality and performance of cutting-edge semiconductor devices.

• Lead FPGA design from architecture through implementation and bring-up, including requirements definition, trade-off analysis, timing closure, resource optimization, and performance tuning.
• Develop high-performance FPGA solutions involving complex interfaces and subsystem integration, along with automation and debug tools using TCL and Python.
• Collaborate with hardware, software, systems, and design verification teams to deliver cohesive system-level solutions and achieve appropriate simulation and test coverage.
• Build and execute validation strategies, including lab bring-up, debug, and root cause analysis using JTAG and lab instrumentation.
• Partner on PCB and system design decisions that affect FPGA performance and integration.
• Mentor junior engineers and serve as the technical lead for FPGA project teams.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

• 8+ years of hands-on experience in FPGA design and development.
• Deep expertise in Verilog/SystemVerilog for design and debugging.
• Proven experience with AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure.
• Strong understanding of digital design fundamentals and the ability to interpret schematics.
• Experience with high-speed interfaces such as PCIe, DDR, SerDes, or similar technologies, and with protocols such as AXI4, USB, I2C, and SPI.
• Demonstrated ability to bring up and debug FPGA designs on hardware platforms.
• Scripting proficiency in TCL and Python for automation and tooling, plus experience with version control systems and collaborative development workflows.
• Strong system-level thinking, sound architectural judgment, and the ability to debug across FPGA, board, and software boundaries.
• Excellent communication, collaboration, technical leadership, and mentoring skills in cross-functional environments.
• Preferred: experience with SystemVerilog-based verification methodologies such as UVM; FPGA SoCs and embedded processor subsystems; ATE or measurement equipment design; signal integrity, high-speed serial interfaces, and transceivers; DDR, HBM, and Flash memory technologies; or AI tools for engineering design.

We are only considering candidates local to the position location and are unable to provide relocation for this position.

This position is not eligible for visa sponsorship.

Compensation:

The base salary range for this role is $154,900 - $247,800 This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan:

This job is eligible for discretionary bonus(es) based on financial performance.

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

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